forked from Imagelibrary/rtems
661 lines
14 KiB
C
661 lines
14 KiB
C
/**
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* @file
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*
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* @ingroup powerpc_shared
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*
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* @brief General purpose assembler macros, linker command file support and
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* some inline functions for direct register access.
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*/
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/*
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* Copyright (c) 2008
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* Embedded Brains GmbH
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* Obere Lagerstr. 30
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* D-82178 Puchheim
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* Germany
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* rtems@embedded-brains.de
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*
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* access function for Device Control Registers inspired by "ppc405common.h"
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* from Michael Hamel ADInstruments May 2008
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*
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* The license and distribution terms for this file may be found in the file
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* LICENSE in this distribution or at http://www.rtems.com/license/LICENSE.
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*/
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/**
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* @defgroup powerpc_shared Shared PowerPC Code
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*/
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#ifndef __LIBCPU_POWERPC_UTILITY_H
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#define __LIBCPU_POWERPC_UTILITY_H
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#if !defined(ASM)
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#include <rtems.h>
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#endif
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#include <rtems/score/cpu.h>
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#include <rtems/powerpc/registers.h>
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#include <rtems/powerpc/powerpc.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if !defined(ASM)
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#include <rtems/bspIo.h>
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#include <rtems/system.h>
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#include <libcpu/cpuIdent.h>
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#define LINKER_SYMBOL(sym) extern char sym []
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/**
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* @brief Read one byte from @a src.
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*/
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static inline uint8_t ppc_read_byte(const volatile void *src)
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{
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uint8_t value;
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asm volatile (
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"lbz %0, 0(%1)"
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: "=r" (value)
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: "b" (src)
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);
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return value;
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}
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/**
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* @brief Read one half word from @a src.
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*/
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static inline uint16_t ppc_read_half_word(const volatile void *src)
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{
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uint16_t value;
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asm volatile (
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"lhz %0, 0(%1)"
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: "=r" (value)
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: "b" (src)
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);
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return value;
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}
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/**
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* @brief Read one word from @a src.
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*/
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static inline uint32_t ppc_read_word(const volatile void *src)
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{
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uint32_t value;
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asm volatile (
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"lwz %0, 0(%1)"
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: "=r" (value)
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: "b" (src)
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);
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return value;
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}
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/**
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* @brief Write one byte @a value to @a dest.
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*/
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static inline void ppc_write_byte(uint8_t value, volatile void *dest)
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{
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asm volatile (
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"stb %0, 0(%1)"
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:
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: "r" (value), "b" (dest)
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);
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}
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/**
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* @brief Write one half word @a value to @a dest.
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*/
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static inline void ppc_write_half_word(uint16_t value, volatile void *dest)
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{
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asm volatile (
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"sth %0, 0(%1)"
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:
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: "r" (value), "b" (dest)
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);
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}
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/**
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* @brief Write one word @a value to @a dest.
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*/
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static inline void ppc_write_word(uint32_t value, volatile void *dest)
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{
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asm volatile (
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"stw %0, 0(%1)" :
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: "r" (value), "b" (dest)
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);
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}
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static inline void *ppc_stack_pointer(void)
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{
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void *sp;
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asm volatile (
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"mr %0, 1"
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: "=r" (sp)
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);
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return sp;
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}
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static inline void ppc_set_stack_pointer(void *sp)
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{
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asm volatile (
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"mr 1, %0"
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:
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: "r" (sp)
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);
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}
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static inline void *ppc_link_register(void)
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{
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void *lr;
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asm volatile (
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"mflr %0"
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: "=r" (lr)
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);
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return lr;
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}
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static inline void ppc_set_link_register(void *lr)
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{
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asm volatile (
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"mtlr %0"
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:
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: "r" (lr)
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);
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}
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static inline uint32_t ppc_machine_state_register(void)
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{
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uint32_t msr;
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asm volatile (
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"mfmsr %0"
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: "=r" (msr)
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);
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return msr;
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}
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static inline void ppc_set_machine_state_register(uint32_t msr)
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{
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asm volatile (
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"mtmsr %0"
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:
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: "r" (msr)
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);
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}
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static inline void ppc_synchronize_data(void)
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{
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RTEMS_COMPILER_MEMORY_BARRIER();
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asm volatile ("sync");
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}
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static inline void ppc_synchronize_instructions(void)
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{
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RTEMS_COMPILER_MEMORY_BARRIER();
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asm volatile ("isync");
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}
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/**
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* @brief Enables external exceptions.
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*
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* You can use this function to enable the external exceptions and restore the
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* machine state with ppc_external_exceptions_disable() later.
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*/
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static inline uint32_t ppc_external_exceptions_enable(void)
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{
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uint32_t current_msr;
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uint32_t new_msr;
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RTEMS_COMPILER_MEMORY_BARRIER();
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asm volatile (
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"mfmsr %0;"
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"ori %1, %0, 0x8000;"
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"mtmsr %1"
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: "=r" (current_msr), "=r" (new_msr)
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);
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return current_msr;
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}
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/**
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* @brief Restores machine state.
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*
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* @see ppc_external_exceptions_enable()
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*/
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static inline void ppc_external_exceptions_disable(uint32_t msr)
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{
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ppc_set_machine_state_register(msr);
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RTEMS_COMPILER_MEMORY_BARRIER();
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}
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/*
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* Simple spin delay in microsecond units for device drivers.
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* This is very dependent on the clock speed of the target.
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*/
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#if defined(mpx8xx) || defined(mpc860) || defined(mpc821)
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/* Wonderful bookE doesn't have mftb/mftbu; they only
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* define the TBRU/TBRL SPRs so we use these. Luckily,
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* we run in supervisory mode so that should work on
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* all CPUs. In user mode we'd have a problem...
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* 2007/11/30, T.S.
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*
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* OTOH, PSIM currently lacks support for reading
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* SPRs 268/269. You need GDB patch sim/2376 to avoid
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* a crash...
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* OTOH, the MPC8xx do not allow to read the timebase registers via mfspr.
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* we NEED a mftb to access the time base.
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* 2009/10/30 Th. D.
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*/
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#define CPU_Get_timebase_low( _value ) \
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asm volatile( "mftb %0" : "=r" (_value) )
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#else
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#define CPU_Get_timebase_low( _value ) \
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asm volatile( "mfspr %0,268" : "=r" (_value) )
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#endif
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/* Must be provided for rtems_bsp_delay to work */
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extern uint32_t bsp_clicks_per_usec;
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#define rtems_bsp_delay( _microseconds ) \
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do { \
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uint32_t start, ticks, now; \
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CPU_Get_timebase_low( start ) ; \
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ticks = (_microseconds) * bsp_clicks_per_usec; \
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do \
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CPU_Get_timebase_low( now ) ; \
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while (now - start < ticks); \
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} while (0)
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#define rtems_bsp_delay_in_bus_cycles( _cycles ) \
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do { \
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uint32_t start, now; \
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CPU_Get_timebase_low( start ); \
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do \
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CPU_Get_timebase_low( now ); \
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while (now - start < (_cycles)); \
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} while (0)
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/*
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* Routines to access the decrementer register
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*/
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#define PPC_Set_decrementer( _clicks ) \
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do { \
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asm volatile( "mtdec %0" : : "r" ((_clicks)) ); \
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} while (0)
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#define PPC_Get_decrementer( _clicks ) \
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asm volatile( "mfdec %0" : "=r" (_clicks) )
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/*
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* Routines to access the time base register
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*/
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static inline uint64_t PPC_Get_timebase_register( void )
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{
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uint32_t tbr_low;
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uint32_t tbr_high;
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uint32_t tbr_high_old;
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uint64_t tbr;
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do {
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#if defined(mpx8xx) || defined(mpc860) || defined(mpc821)
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/* See comment above (CPU_Get_timebase_low) */
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asm volatile( "mftbu %0" : "=r" (tbr_high_old));
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asm volatile( "mftb %0" : "=r" (tbr_low));
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asm volatile( "mftbu %0" : "=r" (tbr_high));
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#else
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asm volatile( "mfspr %0, 269" : "=r" (tbr_high_old));
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asm volatile( "mfspr %0, 268" : "=r" (tbr_low));
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asm volatile( "mfspr %0, 269" : "=r" (tbr_high));
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#endif
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} while ( tbr_high_old != tbr_high );
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tbr = tbr_high;
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tbr <<= 32;
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tbr |= tbr_low;
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return tbr;
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}
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static inline void PPC_Set_timebase_register (uint64_t tbr)
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{
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uint32_t tbr_low;
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uint32_t tbr_high;
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tbr_low = (uint32_t) tbr;
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tbr_high = (uint32_t) (tbr >> 32);
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asm volatile( "mtspr 284, %0" : : "r" (tbr_low));
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asm volatile( "mtspr 285, %0" : : "r" (tbr_high));
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}
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static inline uint32_t ppc_decrementer_register(void)
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{
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uint32_t dec;
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PPC_Get_decrementer(dec);
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return dec;
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}
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static inline void ppc_set_decrementer_register(uint32_t dec)
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{
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PPC_Set_decrementer(dec);
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}
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/**
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* @brief Preprocessor magic for stringification of @a x.
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*/
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#define PPC_STRINGOF(x) #x
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/**
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* @brief Returns the value of the Special Purpose Register with number @a spr.
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*
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* @note This macro uses a GNU C extension.
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*/
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#define PPC_SPECIAL_PURPOSE_REGISTER(spr) \
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({ \
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uint32_t val; \
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asm volatile (\
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"mfspr %0, " PPC_STRINGOF(spr) \
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: "=r" (val) \
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); \
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val;\
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} )
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/**
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* @brief Sets the Special Purpose Register with number @a spr to the value in
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* @a val.
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*/
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#define PPC_SET_SPECIAL_PURPOSE_REGISTER(spr, val) \
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do { \
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asm volatile (\
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"mtspr " PPC_STRINGOF(spr) ", %0" \
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: \
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: "r" (val) \
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); \
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} while (0)
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/**
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* @brief Sets in the Special Purpose Register with number @a spr all bits
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* which are set in @a bits.
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*
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* Interrupts are disabled throughout this operation.
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*/
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#define PPC_SET_SPECIAL_PURPOSE_REGISTER_BITS(spr, bits) \
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do { \
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rtems_interrupt_level level; \
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uint32_t val; \
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uint32_t mybits = bits; \
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rtems_interrupt_disable(level); \
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val = PPC_SPECIAL_PURPOSE_REGISTER(spr); \
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val |= mybits; \
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PPC_SET_SPECIAL_PURPOSE_REGISTER(spr, val); \
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rtems_interrupt_enable(level); \
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} while (0)
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/**
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* @brief Sets in the Special Purpose Register with number @a spr all bits
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* which are set in @a bits. The previous register value will be masked with
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* @a mask.
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*
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* Interrupts are disabled throughout this operation.
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*/
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#define PPC_SET_SPECIAL_PURPOSE_REGISTER_BITS_MASKED(spr, bits, mask) \
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do { \
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rtems_interrupt_level level; \
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uint32_t val; \
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uint32_t mybits = bits; \
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uint32_t mymask = mask; \
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rtems_interrupt_disable(level); \
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val = PPC_SPECIAL_PURPOSE_REGISTER(spr); \
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val &= ~mymask; \
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val |= mybits; \
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PPC_SET_SPECIAL_PURPOSE_REGISTER(spr, val); \
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rtems_interrupt_enable(level); \
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} while (0)
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/**
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* @brief Clears in the Special Purpose Register with number @a spr all bits
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* which are set in @a bits.
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*
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* Interrupts are disabled throughout this operation.
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*/
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#define PPC_CLEAR_SPECIAL_PURPOSE_REGISTER_BITS(spr, bits) \
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do { \
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rtems_interrupt_level level; \
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uint32_t val; \
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uint32_t mybits = bits; \
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rtems_interrupt_disable(level); \
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val = PPC_SPECIAL_PURPOSE_REGISTER(spr); \
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val &= ~mybits; \
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PPC_SET_SPECIAL_PURPOSE_REGISTER(spr, val); \
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rtems_interrupt_enable(level); \
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} while (0)
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/**
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* @brief Returns the value of the Device Control Register with number @a dcr.
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*
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* The PowerPC 4XX family has Device Control Registers.
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*
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* @note This macro uses a GNU C extension.
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*/
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#define PPC_DEVICE_CONTROL_REGISTER(dcr) \
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({ \
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uint32_t val; \
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asm volatile (\
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"mfdcr %0, " PPC_STRINGOF(dcr) \
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: "=r" (val) \
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); \
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val;\
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} )
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/**
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* @brief Sets the Device Control Register with number @a dcr to the value in
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* @a val.
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*
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* The PowerPC 4XX family has Device Control Registers.
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*/
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#define PPC_SET_DEVICE_CONTROL_REGISTER(dcr, val) \
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do { \
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asm volatile (\
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"mtdcr " PPC_STRINGOF(dcr) ", %0" \
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: \
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: "r" (val) \
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); \
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} while (0)
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/**
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* @brief Sets in the Device Control Register with number @a dcr all bits
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* which are set in @a bits.
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*
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* Interrupts are disabled throughout this operation.
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*/
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#define PPC_SET_DEVICE_CONTROL_REGISTER_BITS(dcr, bits) \
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do { \
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rtems_interrupt_level level; \
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uint32_t val; \
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uint32_t mybits = bits; \
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rtems_interrupt_disable(level); \
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val = PPC_DEVICE_CONTROL_REGISTER(dcr); \
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val |= mybits; \
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PPC_SET_DEVICE_CONTROL_REGISTER(dcr, val); \
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rtems_interrupt_enable(level); \
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} while (0)
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/**
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* @brief Sets in the Device Control Register with number @a dcr all bits
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* which are set in @a bits. The previous register value will be masked with
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* @a mask.
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*
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* Interrupts are disabled throughout this operation.
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*/
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#define PPC_SET_DEVICE_CONTROL_REGISTER_BITS_MASKED(dcr, bits, mask) \
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do { \
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rtems_interrupt_level level; \
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uint32_t val; \
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uint32_t mybits = bits; \
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uint32_t mymask = mask; \
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rtems_interrupt_disable(level); \
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val = PPC_DEVICE_CONTROL_REGISTER(dcr); \
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val &= ~mymask; \
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val |= mybits; \
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PPC_SET_DEVICE_CONTROL_REGISTER(dcr, val); \
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rtems_interrupt_enable(level); \
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} while (0)
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/**
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* @brief Clears in the Device Control Register with number @a dcr all bits
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* which are set in @a bits.
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*
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* Interrupts are disabled throughout this operation.
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*/
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#define PPC_CLEAR_DEVICE_CONTROL_REGISTER_BITS(dcr, bits) \
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do { \
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rtems_interrupt_level level; \
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uint32_t val; \
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uint32_t mybits = bits; \
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rtems_interrupt_disable(level); \
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val = PPC_DEVICE_CONTROL_REGISTER(dcr); \
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val &= ~mybits; \
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PPC_SET_DEVICE_CONTROL_REGISTER(dcr, val); \
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rtems_interrupt_enable(level); \
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} while (0)
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static inline uint32_t ppc_time_base(void)
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{
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uint32_t val;
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CPU_Get_timebase_low(val);
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return val;
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}
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static inline void ppc_set_time_base(uint32_t val)
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{
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PPC_SET_SPECIAL_PURPOSE_REGISTER(TBWL, val);
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}
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static inline uint32_t ppc_time_base_upper(void)
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|
{
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return PPC_SPECIAL_PURPOSE_REGISTER(TBRU);
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|
}
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|
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static inline void ppc_set_time_base_upper(uint32_t val)
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|
{
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PPC_SET_SPECIAL_PURPOSE_REGISTER(TBWU, val);
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|
}
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|
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static inline uint64_t ppc_time_base_64(void)
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|
{
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|
return PPC_Get_timebase_register();
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|
}
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|
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static inline void ppc_set_time_base_64(uint64_t val)
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|
{
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|
PPC_Set_timebase_register(val);
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|
}
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|
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|
void ppc_code_copy(void *dest, const void *src, size_t n);
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|
|
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#endif /* ifndef ASM */
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|
|
|
#if defined(ASM)
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|
#include <rtems/asm.h>
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|
|
|
.macro LA reg, addr
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|
lis \reg, (\addr)@h
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|
ori \reg, \reg, (\addr)@l
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|
.endm
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|
|
|
.macro LWI reg, value
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|
lis \reg, (\value)@h
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|
ori \reg, \reg, (\value)@l
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|
.endm
|
|
|
|
.macro LW reg, addr
|
|
lis \reg, \addr@ha
|
|
lwz \reg, \addr@l(\reg)
|
|
.endm
|
|
|
|
/*
|
|
* Tests the bits in reg1 against the bits set in mask. A match is indicated
|
|
* by EQ = 0 in CR0. A mismatch is indicated by EQ = 1 in CR0. The register
|
|
* reg2 is used to load the mask.
|
|
*/
|
|
.macro TSTBITS reg1, reg2, mask
|
|
LWI \reg2, \mask
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|
and \reg1, \reg1, \reg2
|
|
cmplw \reg1, \reg2
|
|
.endm
|
|
|
|
.macro SETBITS reg1, reg2, mask
|
|
LWI \reg2, \mask
|
|
or \reg1, \reg1, \reg2
|
|
.endm
|
|
|
|
.macro CLRBITS reg1, reg2, mask
|
|
LWI \reg2, \mask
|
|
andc \reg1, \reg1, \reg2
|
|
.endm
|
|
|
|
.macro GLOBAL_FUNCTION name
|
|
.global \name
|
|
.type \name, @function
|
|
\name:
|
|
.endm
|
|
|
|
/*
|
|
* Obtain interrupt mask
|
|
*/
|
|
.macro GET_INTERRUPT_MASK mask
|
|
mfspr \mask, sprg0
|
|
.endm
|
|
|
|
/*
|
|
* Disables all asynchronous exeptions (interrupts) which may cause a context
|
|
* switch.
|
|
*/
|
|
.macro INTERRUPT_DISABLE level, mask
|
|
mfmsr \level
|
|
GET_INTERRUPT_MASK mask=\mask
|
|
andc \mask, \level, \mask
|
|
mtmsr \mask
|
|
.endm
|
|
|
|
/*
|
|
* Restore previous machine state.
|
|
*/
|
|
.macro INTERRUPT_ENABLE level
|
|
mtmsr \level
|
|
.endm
|
|
|
|
#define LINKER_SYMBOL(sym) .extern sym
|
|
|
|
#endif /* ASM */
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* __LIBCPU_POWERPC_UTILITY_H */
|