forked from Imagelibrary/rtems
511dc4b2be
Statically initialize the interrupt stack area
(_Configuration_Interrupt_stack_area_begin,
_Configuration_Interrupt_stack_area_end, and
_Configuration_Interrupt_stack_size) via <rtems/confdefs.h>. Place the
interrupt stack area in a special section ".rtemsstack.interrupt". Let
BSPs define the optimal placement of this section in their linker
command files (e.g. in a fast on-chip memory).
This change makes makes the CPU_HAS_SOFTWARE_INTERRUPT_STACK and
CPU_HAS_HARDWARE_INTERRUPT_STACK CPU port defines superfluous, since the
low level initialization code has all information available via global
symbols.
This change makes the CPU_ALLOCATE_INTERRUPT_STACK CPU port define
superfluous, since the interrupt stacks are allocated by confdefs.h for
all architectures. There is no need for BSP-specific linker command
file magic (except the section placement), see previous ARM linker
command file as a bad example.
Remove _CPU_Install_interrupt_stack(). Initialize the hardware
interrupt stack in _CPU_Initialize() if necessary (e.g.
m68k_install_interrupt_stack()).
The optional _CPU_Interrupt_stack_setup() is still useful to customize
the registration of the interrupt stack area in the per-CPU information.
The initialization stack can reuse the interrupt stack, since
* interrupts are disabled during the sequential system initialization,
and
* the boot_card() function does not return.
This stack resuse saves memory.
Changes per architecture:
arm:
* Mostly replace the linker symbol based configuration of stacks with
the standard <rtems/confdefs.h> configuration via
CONFIGURE_INTERRUPT_STACK_SIZE. The size of the FIQ, ABT and UND
mode stack is still defined via linker symbols. These modes are
rarely used in applications and the default values provided by the
BSP should be sufficient in most cases.
* Remove the bsp_processor_count linker symbol hack used for the SMP
support. This is possible since the interrupt stack area is now
allocated by the linker and not allocated from the heap. This makes
some configure.ac stuff obsolete. Remove the now superfluous BSP
variants altcycv_devkit_smp and realview_pbx_a9_qemu_smp.
bfin:
* Remove unused magic linker command file allocation of initialization
stack. Maybe a previous linker command file copy and paste problem?
In the start.S the initialization stack is set to a hard coded value.
lm32, m32c, mips, nios2, riscv, sh, v850:
* Remove magic linker command file allocation of initialization stack.
Reuse interrupt stack for initialization stack.
m68k:
* Remove magic linker command file allocation of initialization stack.
Reuse interrupt stack for initialization stack.
powerpc:
* Remove magic linker command file allocation of initialization stack.
Reuse interrupt stack for initialization stack.
* Used dedicated memory region (REGION_RTEMSSTACK) for the interrupt
stack on BSPs using the shared linkcmds.base (replacement for
REGION_RWEXTRA).
sparc:
* Remove the hard coded initialization stack. Use the interrupt stack
for the initialization stack on the boot processor. This saves
16KiB of RAM.
Update #3459.
BSP NAME: TLL6527M
BOARD: TLL6527M
CPU FAMILY: Blackfin
CPU: Blackfin 527
MODE: 32 bit mode
DEBUG MONITOR:
SIMULATOR:
PERIPHERALS
===========
TIMERS: internal
RESOLUTION: 1 milisecond
SERIAL PORTS: 2 internal UART (polled/interrupt/dma)
REAL-TIME CLOCK: internal
DMA: internal
VIDEO: none
SCSI: none
NETWORKING: none
DRIVER INFORMATION
==================
CLOCK DRIVER: internal
TIMER DRIVER: internal
I2C:
SPI:
PPI:
SPORT:
STDIO
=====
PORT: Console port 1
ELECTRICAL: RS-232
BAUD: 9600
BITS PER CHARACTER: 8
PARITY: None
STOP BITS: 1
NOTES
=====
The TLL56527M board contains analog devices blackfin 527 processor. In addition
to the peripherals provided by bf527 the board has a temprature sensor,
accelerometer and power module connected via I2C. It also has LCD interface,
Card reader interface.
The analog device bf52X family of processors are different from the bf53x range
of processors. This port supports the additional features that are not
supported by the blackfin 53X family of processors.
The TLL6527M does not use the interrupt module used by the bfin 53x since it has
an additional system interrupt controller isr registers for additional lines.
On the 53X these line are multiplexed.
The centralized interrupt handler is implemented to use lookup tables for
jumping to the user ISR. For more details look at files implemented under
libcpu/bfin/bf52x/interrupt/*
This port supports only the uart peripheral. The uart is supported via
polling, DMA, interrupt. The uart file is generic and is common between the
ports. Under bsp configure.ac files
* change the CONSOLE_BAUDRATE or to choose among different baudrate.
* Set UART_USE_DMA for UART to use DMA based transfers. In DMA based transfer
chunk of buffer is transmitted at once and then an interrupt is generated.
* Set CONSOLE_USE_INTERRUPTS to use interrupt based transfers. After every
character is transmitted an interrupt is generated.
* If CONSOLE_USE_INTERRUPTS, UART_USE_DMA are both not set then the port uses
polling to transmit data over uart. This call is blocking.
TLL6527 specific file are mentioned below.
=====================================
c/src/lib/libcpu/bfin/bf52x/*
c/src/lib/libbsp/bfin/TLL6527M/*
The port was compiled using
===========================
1. bfin-rtems4.11-gcc (GCC) 4.5.2 20101216
(RTEMS gcc-4.5.2-3.el5/newlib-1.19.0-1.el5)
2. automake (GNU automake) 1.11.1
3. autoconf (GNU Autoconf) 2.68
The port was configured using the flags
==========================================
--target=bfin-rtems4.11 --enable-rtemsbsp=TLL6527M --enable-tests=samples
--disable-posix --disable-itron
ISSUES:
Could not place code in l1code (SRAM) because it was not being loaded by the
gnu loaded.