forked from Imagelibrary/rtems
511dc4b2be
Statically initialize the interrupt stack area
(_Configuration_Interrupt_stack_area_begin,
_Configuration_Interrupt_stack_area_end, and
_Configuration_Interrupt_stack_size) via <rtems/confdefs.h>. Place the
interrupt stack area in a special section ".rtemsstack.interrupt". Let
BSPs define the optimal placement of this section in their linker
command files (e.g. in a fast on-chip memory).
This change makes makes the CPU_HAS_SOFTWARE_INTERRUPT_STACK and
CPU_HAS_HARDWARE_INTERRUPT_STACK CPU port defines superfluous, since the
low level initialization code has all information available via global
symbols.
This change makes the CPU_ALLOCATE_INTERRUPT_STACK CPU port define
superfluous, since the interrupt stacks are allocated by confdefs.h for
all architectures. There is no need for BSP-specific linker command
file magic (except the section placement), see previous ARM linker
command file as a bad example.
Remove _CPU_Install_interrupt_stack(). Initialize the hardware
interrupt stack in _CPU_Initialize() if necessary (e.g.
m68k_install_interrupt_stack()).
The optional _CPU_Interrupt_stack_setup() is still useful to customize
the registration of the interrupt stack area in the per-CPU information.
The initialization stack can reuse the interrupt stack, since
* interrupts are disabled during the sequential system initialization,
and
* the boot_card() function does not return.
This stack resuse saves memory.
Changes per architecture:
arm:
* Mostly replace the linker symbol based configuration of stacks with
the standard <rtems/confdefs.h> configuration via
CONFIGURE_INTERRUPT_STACK_SIZE. The size of the FIQ, ABT and UND
mode stack is still defined via linker symbols. These modes are
rarely used in applications and the default values provided by the
BSP should be sufficient in most cases.
* Remove the bsp_processor_count linker symbol hack used for the SMP
support. This is possible since the interrupt stack area is now
allocated by the linker and not allocated from the heap. This makes
some configure.ac stuff obsolete. Remove the now superfluous BSP
variants altcycv_devkit_smp and realview_pbx_a9_qemu_smp.
bfin:
* Remove unused magic linker command file allocation of initialization
stack. Maybe a previous linker command file copy and paste problem?
In the start.S the initialization stack is set to a hard coded value.
lm32, m32c, mips, nios2, riscv, sh, v850:
* Remove magic linker command file allocation of initialization stack.
Reuse interrupt stack for initialization stack.
m68k:
* Remove magic linker command file allocation of initialization stack.
Reuse interrupt stack for initialization stack.
powerpc:
* Remove magic linker command file allocation of initialization stack.
Reuse interrupt stack for initialization stack.
* Used dedicated memory region (REGION_RTEMSSTACK) for the interrupt
stack on BSPs using the shared linkcmds.base (replacement for
REGION_RWEXTRA).
sparc:
* Remove the hard coded initialization stack. Use the interrupt stack
for the initialization stack on the boot processor. This saves
16KiB of RAM.
Update #3459.
151 lines
4.0 KiB
ArmAsm
151 lines
4.0 KiB
ArmAsm
/*
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* Cogent CSB336 startup code
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*
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* Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com>
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#include <rtems/asm.h>
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#include <rtems/score/cpu.h>
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.section .bsp_start_text,"ax"
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.code 32
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_start_jump_at_origin:
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ldr pc, _start_address
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_start_address:
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.word _start
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.text
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.globl _start
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_start:
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/*
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* Since I don't plan to return to the bootloader,
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* I don't have to save the registers.
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*/
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/* Set end of interrupt stack area */
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ldr r7, =_Configuration_Interrupt_stack_area_end
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/* Enter FIQ mode and set up the FIQ stack pointer */
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mov r0, #(ARM_PSR_M_FIQ | ARM_PSR_I | ARM_PSR_F)
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msr cpsr, r0
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ldr r1, =bsp_stack_fiq_size
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mov sp, r7
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sub r7, r7, r1
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/* Enter ABT mode and set up the ABT stack pointer */
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mov r0, #(ARM_PSR_M_ABT | ARM_PSR_I | ARM_PSR_F)
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msr cpsr, r0
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ldr r1, =bsp_stack_abt_size
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mov sp, r7
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sub r7, r7, r1
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/* Enter UND mode and set up the UND stack pointer */
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mov r0, #(ARM_PSR_M_UND | ARM_PSR_I | ARM_PSR_F)
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msr cpsr, r0
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ldr r1, =bsp_stack_und_size
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mov sp, r7
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sub r7, r7, r1
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/* Enter IRQ mode and set up the IRQ stack pointer */
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mov r0, #(ARM_PSR_M_IRQ | ARM_PSR_I | ARM_PSR_F)
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msr cpsr, r0
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mov sp, r7
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/*
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* Enter SVC mode and set up the SVC stack pointer, reuse IRQ stack
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* (interrupts are disabled).
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*/
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mov r0, #(ARM_PSR_M_SVC | ARM_PSR_I | ARM_PSR_F)
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msr cpsr, r0
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mov sp, r7
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/* Stay in SVC mode */
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/* zero the bss */
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ldr r1, =bsp_section_bss_end
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ldr r0, =bsp_section_bss_begin
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_bss_init:
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mov r2, #0
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cmp r0, r1
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strlot r2, [r0], #4
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blo _bss_init /* loop while r0 < r1 */
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/*
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* Initialize the MMU. After we return, the MMU is enabled,
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* and memory may be remapped. I hope we don't remap this
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* memory away.
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*/
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ldr r0, =mem_map
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bl mmu_init
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/*
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* Initialize the exception vectors. This includes the
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* exceptions vectors (0x00000000-0x0000001c), and the
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* pointers to the exception handlers (0x00000020-0x0000003c).
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*/
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mov r0, #0
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adr r1, vector_block
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ldmia r1!, {r2-r9}
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stmia r0!, {r2-r9}
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ldmia r1!, {r2-r9}
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stmia r0!, {r2-r9}
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/* Now we are prepared to start the BSP's C code */
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mov r0, #0
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bl boot_card
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/*
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* Theoretically, we could return to what started us up,
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* but we'd have to have saved the registers and stacks.
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* Instead, we'll just reset.
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*/
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bl bsp_reset
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/* We shouldn't get here. If we do, hang */
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_hang: b _hang
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/*
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* This is the exception vector table and the pointers to
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* the functions that handle the exceptions. It's a total
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* of 16 words (64 bytes)
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*/
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vector_block:
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ldr pc, handler_addr_reset
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ldr pc, handler_addr_undef
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ldr pc, handler_addr_swi
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ldr pc, handler_addr_prefetch
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ldr pc, handler_addr_abort
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nop
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ldr pc, handler_addr_irq
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ldr pc, handler_addr_fiq
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handler_addr_reset:
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.word bsp_reset
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handler_addr_undef:
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.word _ARMV4_Exception_undef_default
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handler_addr_swi:
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.word _ARMV4_Exception_swi_default
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handler_addr_prefetch:
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.word _ARMV4_Exception_pref_abort_default
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handler_addr_abort:
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.word _ARMV4_Exception_data_abort_default
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handler_addr_reserved:
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.word _ARMV4_Exception_reserved_default
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handler_addr_irq:
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.word _ARMV4_Exception_interrupt
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handler_addr_fiq:
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.word _ARMV4_Exception_fiq_default
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