forked from Imagelibrary/rtems
132 lines
5.8 KiB
C
132 lines
5.8 KiB
C
/**
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*@file
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*
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*@brief
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* - This file provides the register address for the 52X model. The file is
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* based on the 533 implementation with some addition to support 52X range of
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* processors.
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*
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* Target: TLL6527v1-0
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* Compiler:
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*
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* COPYRIGHT (c) 2010 by ECE Northeastern University.
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license
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*
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* @author Rohan Kangralkar, ECE, Northeastern University
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* (kangralkar.r@husky.neu.edu)
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*
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* LastChange:
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*/
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#ifndef _BF52X_H_
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#define _BF52X_H_
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/* register (or register block) addresses */
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#define SIC_BASE_ADDRESS 0xffc00100
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#define WDOG_BASE_ADDRESS 0xffc00200
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#define RTC_BASE_ADDRESS 0xffc00300
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#define UART0_BASE_ADDRESS 0xffc00400
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#define UART1_BASE_ADDRESS 0xffc02000
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#define SPI_BASE_ADDRESS 0xffc00500
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#define TIMER_BASE_ADDRESS 0xffc00600
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#define TIMER_CHANNELS 3
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#define TIMER_PITCH 0x10
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#define TIMER0_BASE_ADDRESS 0xffc00600
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#define TIMER1_BASE_ADDRESS 0xffc00610
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#define TIMER2_BASE_ADDRESS 0xffc00620
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#define TIMER_ENABLE 0xffc00640
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#define TIMER_DISABLE 0xffc00644
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#define TIMER_STATUS 0xffc00648
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#define PORTFIO_BASE_ADDRESS 0xffc00700
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#define SPORT0_BASE_ADDRESS 0xffc00800
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#define SPORT1_BASE_ADDRESS 0xffc00900
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#define EBIU_BASE_ADDRESS 0xffc00a00
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#define DMA_TC_PER 0xffc00b0c
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#define DMA_TC_CNT 0xffc00b10
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#define DMA_BASE_ADDRESS 0xffc00c00
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#define DMA_CHANNELS 8
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#define DMA_PITCH 0x40
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#define DMA0_BASE_ADDRESS 0xffc00c00
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#define DMA1_BASE_ADDRESS 0xffc00c40
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#define DMA2_BASE_ADDRESS 0xffc00c80
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#define DMA3_BASE_ADDRESS 0xffc00cc0
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#define DMA4_BASE_ADDRESS 0xffc00d00
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#define DMA5_BASE_ADDRESS 0xffc00d40
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#define DMA6_BASE_ADDRESS 0xffc00d80
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#define DMA7_BASE_ADDRESS 0xffc00dc0
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#define DMA8_BASE_ADDRESS 0xffc00e00
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#define DMA9_BASE_ADDRESS 0xffc00e40
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#define DMA10_BASE_ADDRESS 0xffc00e80
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#define DMA11_BASE_ADDRESS 0xffc00ec0
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#define MDMA_BASE_ADDRESS 0xffc00e00
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#define MDMA_CHANNELS 2
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#define MDMA_D_S 0x40
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#define MDMA_PITCH 0x80
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#define MDMA0D_BASE_ADDRESS 0xffc00e00
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#define MDMA0S_BASE_ADDRESS 0xffc00e40
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#define MDMA1D_BASE_ADDRESS 0xffc00e80
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#define MDMA1S_BASE_ADDRESS 0xffc00ec0
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#define PPI_BASE_ADDRESS 0xffc01000
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/* register fields */
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#define DMA_TC_PER_MDMA_ROUND_ROBIN_PERIOD_MASK 0xf800
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#define DMA_TC_PER_MDMA_ROUND_ROBIN_PERIOD_SHIFT 11
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#define DMA_TC_PER_DAB_TRAFFIC_PERIOD_MASK 0x0700
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#define DMA_TC_PER_DAB_TRAFFIC_PERIOD_SHIFT 8
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#define DMA_TC_PER_DEB_TRAFFIC_PERIOD_MASK 0x00f0
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#define DMA_TC_PER_DEB_TRAFFIC_PERIOD_SHIFT 4
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#define DMA_TC_PER_DCB_TRAFFIC_PERIOD_MASK 0x000f
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#define DMA_TC_PER_DCB_TRAFFIC_PERIOD_SHIFT 0
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#define DMA_TC_CNT_MDMA_ROUND_ROBIN_COUNT_MASK 0xf800
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#define DMA_TC_CNT_MDMA_ROUND_ROBIN_COUNT_SHIFT 11
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#define DMA_TC_CNT_DAB_TRAFFIC_COUNT_MASK 0x0700
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#define DMA_TC_CNT_DAB_TRAFFIC_COUNT_SHIFT 8
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#define DMA_TC_CNT_DEB_TRAFFIC_COUNT_MASK 0x00f0
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#define DMA_TC_CNT_DEB_TRAFFIC_COUNT_SHIFT 4
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#define DMA_TC_CNT_DCB_TRAFFIC_COUNT_MASK 0x000f
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#define DMA_TC_CNT_DCB_TRAFFIC_COUNT_SHIFT 0
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#define TIMER_ENABLE_TIMEN2 0x0004
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#define TIMER_ENABLE_TIMEN1 0x0002
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#define TIMER_ENABLE_TIMEN0 0x0001
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#define TIMER_DISABLE_TIMDIS2 0x0004
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#define TIMER_DISABLE_TIMDIS1 0x0002
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#define TIMER_DISABLE_TIMDIS0 0x0001
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#define TIMER_STATUS_TRUN2 0x00004000
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#define TIMER_STATUS_TRUN1 0x00002000
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#define TIMER_STATUS_TRUN0 0x00001000
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#define TIMER_STATUS_TOVF_ERR2 0x00000040
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#define TIMER_STATUS_TOVF_ERR1 0x00000020
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#define TIMER_STATUS_TOVF_ERR0 0x00000010
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#define TIMER_STATUS_TIMIL2 0x00000004
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#define TIMER_STATUS_TIMIL1 0x00000002
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#define TIMER_STATUS_TIMIL0 0x00000001
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/* Core Event Controller vectors */
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#define CEC_EMULATION_VECTOR 0
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#define CEC_RESET_VECTOR 1
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#define CEC_NMI_VECTOR 2
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#define CEC_EXCEPTIONS_VECTOR 3
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#define CEC_HARDWARE_ERROR_VECTOR 5
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#define CEC_CORE_TIMER_VECTOR 6
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#define CEC_INTERRUPT_BASE_VECTOR 7
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#define CEC_INTERRUPT_COUNT 9
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/* System Interrupt Controller vectors */
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#define SIC_IAR_COUNT 8
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#endif /* _BF52X_H_ */
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