Kinsey Moore 10ef7087f6 aarch64: Use page table level 0 ...

This alters the AArch64 page table generation and mapping code and MMU
configuration to use page table level 0 in addition to levels 1, 2, and
3. This allows the mapping of up to 48 bits of memory space and is the
maximum that can be mapped without relying on additional processor
extensions. Mappings are restricted based on the number of physical
address bits that the CPU supports.

2022-07-21 12:26:35 -05:00

..

bsp

aarch64: Use page table level 0

2022-07-21 12:26:35 -05:00

dev/irq

bsps/aarch64: Restore interrupt nesting

2021-11-10 10:51:40 -06:00