forked from Imagelibrary/rtems
98 lines
2.0 KiB
C
98 lines
2.0 KiB
C
/**
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* @file
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*
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* @brief Information Related to a Zilog Z8530 SCC Chip
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*
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* This include file defines information related to a Zilog Z8530
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* SCC Chip. It is a IO mapped part.
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*/
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/*
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* COPYRIGHT (c) 1989-2011.
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* On-Line Applications Research Corporation (OAR).
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.com/license/LICENSE.
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*/
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#ifndef _RTEMS_ZILOG_Z8530_H
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#define _RTEMS_ZILOG_Z8530_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* macros */
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#define VOL8( ptr ) ((volatile uint8_t *)(ptr))
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#define Z8x30_STATE0 ( z8530 ) \
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{ char *garbage; \
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(garbage) = *(VOL8(z8530)) \
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}
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#define Z8x30_WRITE_CONTROL( z8530, reg, data ) \
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*(VOL8(z8530)) = (reg); \
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*(VOL8(z8530)) = (data)
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#define Z8x30_READ_CONTROL( z8530, reg, data ) \
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*(VOL8(z8530)) = (reg); \
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(data) = *(VOL8(z8530))
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#define Z8x30_WRITE_DATA( z8530, data ) \
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*(VOL8(z8530)) = (data);
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#define Z8x30_READ_DATA( z8530, data ) \
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(data) = *(VOL8(z8530));
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/* RR_0 Bit Definitions */
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#define RR_0_TX_BUFFER_EMPTY 0x04
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#define RR_0_RX_DATA_AVAILABLE 0x01
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/* read registers */
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#define RR_0 0x00
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#define RR_1 0x01
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#define RR_2 0x02
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#define RR_3 0x03
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#define RR_4 0x04
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#define RR_5 0x05
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#define RR_6 0x06
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#define RR_7 0x07
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#define RR_8 0x08
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#define RR_9 0x09
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#define RR_10 0x0A
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#define RR_11 0x0B
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#define RR_12 0x0C
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#define RR_13 0x0D
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#define RR_14 0x0E
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#define RR_15 0x0F
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/* write registers */
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#define WR_0 0x00
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#define WR_1 0x01
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#define WR_2 0x02
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#define WR_3 0x03
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#define WR_4 0x04
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#define WR_5 0x05
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#define WR_6 0x06
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#define WR_7 0x07
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#define WR_8 0x08
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#define WR_9 0x09
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#define WR_10 0x0A
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#define WR_11 0x0B
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#define WR_12 0x0C
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#define WR_13 0x0D
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#define WR_14 0x0E
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#define WR_15 0x0F
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#ifdef __cplusplus
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}
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#endif
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#endif
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