forked from Imagelibrary/rtems
1c06068196
The Pi firmware added a wfe(wait for event), the cores 1-3 wait for the start address being written to the mailbox register, followed by a SEV poke to the mailbox that acts as a wfe wake-up event.
80 lines
1.7 KiB
C
80 lines
1.7 KiB
C
/**
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* @file
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*
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* @ingroup raspberrypi
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*
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* @brief Raspberry pi SMP management functions provided to SuperCore
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*/
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/*
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* Copyright (c) 2016 Pavel Pisa <pisa@cmp.felk.cvut.cz>
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*
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* Czech Technical University in Prague
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* Zikova 1903/4
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* 166 36 Praha 6
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* Czech Republic
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*
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* Reuses some ideas from Rohini Kulkarni <krohini1593@gmail.com>
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* GSoC 2015 project and Altera Cyclone-V SMP code
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* by embedded brains GmbH
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#include <rtems/score/smpimpl.h>
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#include <bsp/start.h>
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#include <bsp/raspberrypi.h>
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#include <bsp.h>
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#include <bsp/arm-cp15-start.h>
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#include <libcpu/arm-cp15.h>
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#include <rtems.h>
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#include <bsp/irq-generic.h>
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#include <assert.h>
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bool _CPU_SMP_Start_processor( uint32_t cpu_index )
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{
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bool started;
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uint32_t cpu_index_self = _SMP_Get_current_processor();
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if (cpu_index != cpu_index_self) {
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BCM2835_REG(BCM2836_MAILBOX_3_WRITE_SET_BASE + 0x10 * cpu_index) = (uint32_t)_start;
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_ARM_Send_event();
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/*
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* Wait for secondary processor to complete its basic initialization so
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* that we can enable the unified L2 cache.
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*/
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started = _Per_CPU_State_wait_for_non_initial_state(cpu_index, 0);
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} else {
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started = false;
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}
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return started;
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}
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uint32_t _CPU_SMP_Initialize(void)
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{
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return 4;
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}
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void _CPU_SMP_Finalize_initialization( uint32_t cpu_count )
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{
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/* Do nothing */
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}
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void _CPU_SMP_Prepare_start_multitasking( void )
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{
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/* Do nothing */
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}
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void _CPU_SMP_Send_interrupt( uint32_t target_cpu_index )
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{
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/* Generates IPI */
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BCM2835_REG(BCM2836_MAILBOX_3_WRITE_SET_BASE +
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0x10 * target_cpu_index) = 0x1;
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}
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