forked from Imagelibrary/rtems
dc0a7df674
PR 1799/bsps * .cvsignore, ChangeLog, Makefile.am, README, bsp_specs, configure.ac, clock/clock-config.c, console/console-config.c, console/uart-bridge-master.c, console/uart-bridge-slave.c, include/.cvsignore, include/bsp.h, include/hwreg_vals.h, include/intercom.h, include/irq.h, include/mmu.h, include/qoriq.h, include/tm27.h, include/tsec-config.h, include/u-boot-config.h, include/uart-bridge.h, irq/irq.c, make/custom/qoriq.inc, make/custom/qoriq_core_0.cfg, make/custom/qoriq_core_1.cfg, make/custom/qoriq_p1020rdb.cfg, network/if_intercom.c, network/network.c, rtc/rtc-config.c, shmsupp/intercom-mpci.c, shmsupp/intercom.c, shmsupp/lock.S, start/start.S, startup/bsppredriverhook.c, startup/bspreset.c, startup/bspstart.c, startup/linkcmds.base, startup/linkcmds.qoriq_core_0, startup/linkcmds.qoriq_core_1, startup/linkcmds.qoriq_p1020rdb, startup/mmu-config.c, startup/mmu-tlb1.S, startup/mmu.c: New files.
342 lines
7.8 KiB
C
342 lines
7.8 KiB
C
/**
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* @file
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*
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* @ingroup QorIQ
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*
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* @brief Interrupt implementation.
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*/
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/*
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* Copyright (c) 2010, 2011 embedded brains GmbH. All rights reserved.
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*
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* embedded brains GmbH
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* Obere Lagerstr. 30
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* 82178 Puchheim
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* Germany
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* <rtems@embedded-brains.de>
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.com/license/LICENSE.
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*
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* $Id$
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*/
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#include <rtems.h>
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#include <libcpu/powerpc-utility.h>
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#include <bsp.h>
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#include <bsp/irq.h>
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#include <bsp/irq-generic.h>
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#include <bsp/vectors.h>
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#include <bsp/utility.h>
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#include <bsp/qoriq.h>
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#define VPR_MSK BSP_BBIT32(0)
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#define VPR_A BSP_BBIT32(1)
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#define VPR_P BSP_BBIT32(8)
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#define VPR_S BSP_BBIT32(9)
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#define VPR_PRIORITY(val) BSP_BFLD32(val, 12, 15)
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#define VPR_PRIORITY_GET(reg) BSP_BFLD32GET(reg, 12, 15)
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#define VPR_PRIORITY_SET(reg, val) BSP_BFLD32SET(reg, val, 12, 15)
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#define VPR_VECTOR(val) BSP_BFLD32(val, 16, 31)
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#define VPR_VECTOR_GET(reg) BSP_BFLD32GET(reg, 16, 31)
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#define VPR_VECTOR_SET(reg, val) BSP_BFLD32SET(reg, val, 16, 31)
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#define GCR_RST BSP_BBIT32(0)
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#define GCR_M BSP_BBIT32(2)
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#define SPURIOUS 0xffff
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static const uint16_t vpr_and_dr_offsets [] = {
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[0] = 0x10200 >> 4,
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[1] = 0x10220 >> 4,
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[2] = 0x10240 >> 4,
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[3] = 0x10260 >> 4,
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[4] = 0x10280 >> 4,
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[5] = 0x102a0 >> 4,
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[6] = 0x102c0 >> 4,
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[7] = 0x102e0 >> 4,
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[8] = 0x10300 >> 4,
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[9] = 0x10320 >> 4,
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[10] = 0x10340 >> 4,
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[11] = 0x10360 >> 4,
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[12] = 0x10380 >> 4,
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[13] = 0x103a0 >> 4,
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[14] = 0x103c0 >> 4,
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[15] = 0x103e0 >> 4,
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[16] = 0x10400 >> 4,
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[17] = 0x10420 >> 4,
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[18] = 0x10440 >> 4,
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[19] = 0x10460 >> 4,
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[20] = 0x10480 >> 4,
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[21] = 0x104a0 >> 4,
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[22] = 0x104c0 >> 4,
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[23] = 0x104e0 >> 4,
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[24] = 0x10500 >> 4,
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[25] = 0x10520 >> 4,
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[26] = 0x10540 >> 4,
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[27] = 0x10560 >> 4,
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[28] = 0x10580 >> 4,
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[29] = 0x105a0 >> 4,
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[30] = 0x105c0 >> 4,
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[31] = 0x105e0 >> 4,
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[32] = 0x10600 >> 4,
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[33] = 0x10620 >> 4,
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[34] = 0x10640 >> 4,
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[35] = 0x10660 >> 4,
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[36] = 0x10680 >> 4,
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[37] = 0x106a0 >> 4,
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[38] = 0x106c0 >> 4,
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[39] = 0x106e0 >> 4,
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[40] = 0x10700 >> 4,
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[41] = 0x10720 >> 4,
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[42] = 0x10740 >> 4,
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[43] = 0x10760 >> 4,
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[44] = 0x10780 >> 4,
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[45] = 0x107a0 >> 4,
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[46] = 0x107c0 >> 4,
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[47] = 0x107e0 >> 4,
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[48] = 0x10800 >> 4,
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[49] = 0x10820 >> 4,
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[50] = 0x10840 >> 4,
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[51] = 0x10860 >> 4,
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[52] = 0x10880 >> 4,
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[53] = 0x108a0 >> 4,
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[54] = 0x108c0 >> 4,
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[55] = 0x108e0 >> 4,
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[56] = 0x10900 >> 4,
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[57] = 0x10920 >> 4,
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[58] = 0x10940 >> 4,
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[59] = 0x10960 >> 4,
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[60] = 0x10980 >> 4,
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[61] = 0x109a0 >> 4,
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[62] = 0x109c0 >> 4,
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[63] = 0x109e0 >> 4,
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[QORIQ_IRQ_EXT_0] = 0x10000 >> 4,
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[QORIQ_IRQ_EXT_1] = 0x10020 >> 4,
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[QORIQ_IRQ_EXT_2] = 0x10040 >> 4,
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[QORIQ_IRQ_EXT_3] = 0x10060 >> 4,
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[QORIQ_IRQ_EXT_4] = 0x10080 >> 4,
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[QORIQ_IRQ_EXT_5] = 0x100a0 >> 4,
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[QORIQ_IRQ_EXT_6] = 0x100c0 >> 4,
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[QORIQ_IRQ_EXT_7] = 0x100e0 >> 4,
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[QORIQ_IRQ_EXT_8] = 0x10100 >> 4,
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[QORIQ_IRQ_EXT_9] = 0x10120 >> 4,
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[QORIQ_IRQ_EXT_10] = 0x10140 >> 4,
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[QORIQ_IRQ_EXT_11] = 0x10160 >> 4,
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[QORIQ_IRQ_IPI_0] = 0x010a0 >> 4,
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[QORIQ_IRQ_IPI_1] = 0x010b0 >> 4,
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[QORIQ_IRQ_IPI_2] = 0x010c0 >> 4,
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[QORIQ_IRQ_IPI_3] = 0x010d0 >> 4,
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[QORIQ_IRQ_MI_0] = 0x11600 >> 4,
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[QORIQ_IRQ_MI_1] = 0x11620 >> 4,
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[QORIQ_IRQ_MI_2] = 0x11640 >> 4,
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[QORIQ_IRQ_MI_3] = 0x11660 >> 4,
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[QORIQ_IRQ_MI_4] = 0x11680 >> 4,
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[QORIQ_IRQ_MI_5] = 0x116a0 >> 4,
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[QORIQ_IRQ_MI_6] = 0x116c0 >> 4,
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[QORIQ_IRQ_MI_7] = 0x116e0 >> 4,
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[QORIQ_IRQ_MSI_0] = 0x11c00 >> 4,
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[QORIQ_IRQ_MSI_1] = 0x11c20 >> 4,
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[QORIQ_IRQ_MSI_2] = 0x11c40 >> 4,
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[QORIQ_IRQ_MSI_3] = 0x11c60 >> 4,
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[QORIQ_IRQ_MSI_4] = 0x11c80 >> 4,
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[QORIQ_IRQ_MSI_5] = 0x11ca0 >> 4,
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[QORIQ_IRQ_MSI_6] = 0x11cc0 >> 4,
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[QORIQ_IRQ_MSI_7] = 0x11ce0 >> 4,
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[QORIQ_IRQ_GT_A_0] = 0x01120 >> 4,
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[QORIQ_IRQ_GT_A_1] = 0x01160 >> 4,
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[QORIQ_IRQ_GT_A_2] = 0x011a0 >> 4,
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[QORIQ_IRQ_GT_A_3] = 0x011e0 >> 4,
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[QORIQ_IRQ_GT_B_0] = 0x02120 >> 4,
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[QORIQ_IRQ_GT_B_1] = 0x02160 >> 4,
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[QORIQ_IRQ_GT_B_2] = 0x021a0 >> 4,
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[QORIQ_IRQ_GT_B_3] = 0x021e0 >> 4
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};
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rtems_status_code qoriq_pic_set_priority(
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rtems_vector_number vector,
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int new_priority,
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int *old_priority
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)
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{
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rtems_status_code sc = RTEMS_SUCCESSFUL;
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uint32_t old_vpr = 0;
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if (bsp_interrupt_is_valid_vector(vector)) {
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int offs = vpr_and_dr_offsets [vector] << 2;
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volatile uint32_t *vpr = (volatile uint32_t *) &qoriq.pic + offs;
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if (QORIQ_PIC_PRIORITY_IS_VALID(new_priority)) {
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rtems_interrupt_level level;
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rtems_interrupt_disable(level);
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old_vpr = *vpr;
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*vpr = VPR_PRIORITY_SET(old_vpr, (uint32_t) new_priority);
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rtems_interrupt_enable(level);
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} else if (new_priority < 0) {
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old_vpr = *vpr;
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} else {
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sc = RTEMS_INVALID_PRIORITY;
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}
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} else {
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sc = RTEMS_INVALID_ID;
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}
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if (old_priority != NULL) {
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*old_priority = (int) VPR_PRIORITY_GET(old_vpr);
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}
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return sc;
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}
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rtems_status_code qoriq_pic_set_affinity(
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rtems_vector_number vector,
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uint32_t processor_index
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)
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{
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rtems_status_code sc = RTEMS_SUCCESSFUL;
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if (bsp_interrupt_is_valid_vector(vector)) {
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if (processor_index <= 1) {
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int offs = (vpr_and_dr_offsets [vector] << 2) + 4;
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volatile uint32_t *dr = (volatile uint32_t *) &qoriq.pic + offs;
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*dr = BSP_BIT32(processor_index);
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} else {
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sc = RTEMS_INVALID_NUMBER;
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}
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} else {
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sc = RTEMS_INVALID_ID;
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}
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return sc;
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}
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static rtems_status_code pic_vector_enable(rtems_vector_number vector, uint32_t msk)
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{
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rtems_status_code sc = RTEMS_SUCCESSFUL;
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if (bsp_interrupt_is_valid_vector(vector)) {
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int offs = vpr_and_dr_offsets [vector] << 2;
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volatile uint32_t *vpr = (volatile uint32_t *) &qoriq.pic + offs;
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rtems_interrupt_level level;
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rtems_interrupt_disable(level);
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*vpr = (*vpr & ~VPR_MSK) | msk;
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rtems_interrupt_enable(level);
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}
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return sc;
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}
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rtems_status_code bsp_interrupt_vector_enable(rtems_vector_number vector)
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{
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return pic_vector_enable(vector, 0);
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}
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rtems_status_code bsp_interrupt_vector_disable(rtems_vector_number vector)
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{
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return pic_vector_enable(vector, VPR_MSK);
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}
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static int qoriq_external_exception_handler(BSP_Exception_frame *frame, unsigned exception_number)
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{
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rtems_vector_number vector = qoriq.pic.iack;
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if (vector != SPURIOUS) {
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uint32_t msr = ppc_external_exceptions_enable();
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bsp_interrupt_handler_dispatch(vector);
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ppc_external_exceptions_disable(msr);
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qoriq.pic.eoi = 0;
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qoriq.pic.whoami;
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} else {
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bsp_interrupt_handler_default(vector);
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}
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return 0;
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}
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static bool pic_is_ipi(rtems_vector_number vector)
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{
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return QORIQ_IRQ_IPI_0 <= vector && vector <= QORIQ_IRQ_IPI_3;
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}
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static void pic_reset(void)
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{
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qoriq.pic.gcr = GCR_RST;
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while ((qoriq.pic.gcr & GCR_RST) != 0) {
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/* Wait */
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}
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}
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static void pic_global_timer_init(void)
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{
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int i = 0;
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qoriq.pic.tcra = 0;
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qoriq.pic.tcrb = 0;
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for (i = 0; i < 4; ++i) {
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qoriq.pic.gta [0].bcr = GTBCR_CI;
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qoriq.pic.gtb [0].bcr = GTBCR_CI;
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}
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}
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rtems_status_code bsp_interrupt_facility_initialize(void)
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{
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rtems_vector_number i = 0;
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uint32_t processor_id = ppc_processor_id();
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if (ppc_exc_set_handler(ASM_EXT_VECTOR, qoriq_external_exception_handler)) {
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return RTEMS_IO_ERROR;
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}
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if (processor_id == 0) {
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/* Core 0 must do the basic initialization */
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pic_reset();
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for (i = BSP_INTERRUPT_VECTOR_MIN; i <= BSP_INTERRUPT_VECTOR_MAX; ++i) {
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volatile uint32_t *base = (volatile uint32_t *) &qoriq.pic;
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int offs = vpr_and_dr_offsets [i] << 2;
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volatile uint32_t *vpr = base + offs;
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*vpr = VPR_MSK | VPR_P | VPR_PRIORITY(1) | VPR_VECTOR(i);
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if (!pic_is_ipi(i)) {
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volatile uint32_t *dr = base + offs + 4;
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*dr = 0x1;
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}
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}
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qoriq.pic.mer03 = 0xf;
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qoriq.pic.mer47 = 0xf;
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qoriq.pic.svr = SPURIOUS;
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qoriq.pic.gcr = GCR_M;
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pic_global_timer_init();
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}
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qoriq.pic.ctpr = 0;
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for (i = BSP_INTERRUPT_VECTOR_MIN; i <= BSP_INTERRUPT_VECTOR_MAX; ++i) {
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qoriq.pic.iack;
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qoriq.pic.eoi = 0;
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qoriq.pic.whoami;
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}
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return RTEMS_SUCCESSFUL;
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}
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void bsp_interrupt_handler_default(rtems_vector_number vector)
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{
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printk("Spurious interrupt: 0x%08x\n", vector);
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}
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