forked from Imagelibrary/rtems
11c2382d67
* mpc505/vectors/vectors.S: Include <rtems/asm.h> instead of <asm.h>. * mpc6xx/exceptions/asm_utils.S: Include <rtems/asm.h> instead of <asm.h>. * mpc6xx/mmu/mmuAsm.S: Include <rtems/asm.h> instead of <asm.h>. * mpc8260/exceptions/asm_utils.S: Include <rtems/asm.h> instead of <asm.h>. * mpc8xx/exceptions/asm_utils.S: Include <rtems/asm.h> instead of <asm.h>. * ppc403/vectors/vectors.S: Include <rtems/asm.h> instead of <asm.h>. * mpc5xx/exceptions/asm_utils.S: Include <rtems/asm.h> instead of <asm.h>. * mpc8260/clock/clock.c: Include <rtems/clockdrv.h> instead of <clockdrv.h>. * mpc8xx/clock/clock.c: Include <rtems/clockdrv.h> instead of <clockdrv.h>. * ppc403/clock/clock.c: Include <rtems/clockdrv.h> instead of <clockdrv.h>.
65 lines
1.4 KiB
ArmAsm
65 lines
1.4 KiB
ArmAsm
/*
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* asm_utils.s
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*
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* asm_utils.S,v 1.2 2002/04/18 20:55:37 joel Exp
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*
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* Copyright (C) 1999 Eric Valette (valette@crf.canon.fr)
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*
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* This file contains the low-level support for moving exception
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* exception code to appropriate location.
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*
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* Adapted for MPC5XX Wilfried Busalski (w.busalski@lancier-monitoring.de)
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* (C) Lancier Monitoring GmbH
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*/
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#include <rtems/asm.h>
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#include <rtems/score/cpu.h>
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#include <libcpu/io.h>
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//SPR defines
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#define SPR_ICCST 560
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.globl codemove
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codemove:
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.type codemove,@function
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/* r3 dest, r4 src, r5 length in bytes, r6 cachelinesize */
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cmplw cr1,r3,r4
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addi r0,r5,3
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srwi. r0,r0,2
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beq cr1,4f /* In place copy is not necessary */
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beq 7f /* Protect against 0 count */
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mtctr r0
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bge cr1,2f
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la r8,-4(r4)
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la r7,-4(r3)
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1: lwzu r0,4(r8)
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stwu r0,4(r7)
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bdnz 1b
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b 4f
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2: slwi r0,r0,2
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add r8,r4,r0
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add r7,r3,r0
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3: lwzu r0,-4(r8)
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stwu r0,-4(r7)
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bdnz 3b
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/* Now flush the cache: note that we must start from a cache aligned
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* address. Otherwise we might miss one cache line.
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*/
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4: lis r0, 0x0A00 // Command Unlock All
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mtspr SPR_ICCST, r0 // Cache Unlock ALL
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lis r0, 0x0C00 // Command Invalidate All
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mtspr SPR_ICCST, r0 // Cache Invalidate ALL
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lis r0, 0x0200 // Command Enable All
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mtspr SPR_ICCST, r0 // Cache Enable ALL
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7: sync /* Wait for all icbi to complete on bus */
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isync
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blr
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