forked from Imagelibrary/rtems
65 lines
1.9 KiB
C
65 lines
1.9 KiB
C
/**
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* @file
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*
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* @ingroup arm_beagle
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*
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* @brief Support for eQEP for the BeagleBone Black.
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*/
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/**
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* Copyright (c) 2020 James Fitzsimons <james.fitzsimons@gmail.com>
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#include <libcpu/am335x.h>
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#include <stdio.h>
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#include <bsp.h>
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#include <bsp/pwmss.h>
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#include <bsp/beagleboneblack.h>
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/**
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* @brief This function configures the L3 and L4_PER system clocks.
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* It also configures the system clocks for the specified ePWMSS
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* instance.
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*
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* @param pwmss_id The instance number of ePWMSS whose system clocks
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* have to be configured.
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*
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* 'pwmss_id' can take one of the following values:
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* (0 <= pwmss_id <= 2)
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*
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* @return True if successful
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* False if Unsuccessful
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*/
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rtems_status_code pwmss_module_clk_config(BBB_PWMSS pwmss_id)
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{
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uint32_t clkctrl;
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/* calculate the address of the clock control register for the PWMSS
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* module we are configuring */
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if(pwmss_id == BBB_PWMSS0) {
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clkctrl = AM335X_CM_PER_ADDR + AM335X_CM_PER_EPWMSS0_CLKCTRL;
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} else if(pwmss_id == BBB_PWMSS1) {
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clkctrl = AM335X_CM_PER_ADDR + AM335X_CM_PER_EPWMSS1_CLKCTRL;
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} else if(pwmss_id == BBB_PWMSS2) {
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clkctrl = AM335X_CM_PER_ADDR + AM335X_CM_PER_EPWMSS2_CLKCTRL;
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}
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/* when the module is functional the IDLEST bits (16 -17) of the
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* CM_PER_EPWMSSx_CLKCTRL register will be 0x0. */
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const uint32_t is_functional = 0x0;
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const uint32_t idle_bits = AM335X_CM_PER_EPWMSSx_CLKCTRL_IDLEST;
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const uint32_t is_enable = AM335X_CM_PER_EPWMSSx_CLKCTRL_MODULEMODE_ENABLE;
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const uint32_t module_mode = AM335X_CM_PER_EPWMSSx_CLKCTRL_MODULEMODE;
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REG(clkctrl) |= is_enable;
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while((REG(clkctrl) & module_mode) != is_enable);
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while((REG(clkctrl) & idle_bits) != is_functional);
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return RTEMS_SUCCESSFUL;
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}
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