forked from Imagelibrary/rtems
206 lines
8.4 KiB
Plaintext
206 lines
8.4 KiB
Plaintext
# RTEMS generic mcf548x BSP
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#
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# Copyright (c) 2007 embedded brains GmbH & Co. KG
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#
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# Parts of the code has been derived from the "dBUG source code"
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# package Freescale is providing for M548X EVBs. The usage of
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# the modified or unmodified code and it's integration into the
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# generic mcf548x BSP has been done according to the Freescale
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# license terms.
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#
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# The Freescale license terms can be reviewed in the file
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#
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# LICENSE.Freescale
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#
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# The generic mcf548x BSP has been developed on the basic
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# structures and modules of the av5282 BSP.
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#
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# The license and distribution terms for this file may be
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# found in the file LICENSE in this distribution or at
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# http://www.rtems.org/license/LICENSE.
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Description: Generic mcf548x BSP
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The genmcf548x supports several boards based on the Freescale MCF547x/8x
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ColdFire microcontrollers
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Supported Hardware: mcf5484FireEngine
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=============================
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CPU: MCF548x, 200MHz
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XLB: 100 MHz, which is the main clock for all onchip peripherals
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RAM: 64M (m5484FireEngine)
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Boot-Flash: 2M (m5484FireEngine)
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Code-Flash: 16M (m5484FireEngine)
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Core-SRAM: 8K
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Core-SysRAM: 32K
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Boot-Monitor:None
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Supported Hardware: COBRA5475
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=============================
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CPU: MCF5475, 266MHz
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XLB: 132 MHz, which is the main clock for all onchip peripherals
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RAM: 128M
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Boot-Flash: 32M
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Core-SRAM: 8K
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Core-SysRAM: 32K
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Boot-Monitor:DBug
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ACKNOWLEDGEMENTS:
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=================
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This BSP is based on the
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av5282 BSP
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and the work of
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D. Peter Siddons
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Brett Swimley
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Jay Monkman
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Eric Norum
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Mike Bertosh
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BSP INFO:
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=========
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BSP NAME: genmcf548x
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BOARD: various MCF547x/8x based boards
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CPU FAMILY: ColdFire 548x
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CPU: MCF5475/MCF5484
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FPU: MCF548x FPU, context switch supported by RTEMS multitasking
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EMAC: MCF548x EMAC context switch supported by RTEMS multitasking (handeld together with FPU context)
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PERIPHERALS
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===========
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TIMERS: 2 slice timers, 4 general purpose timers (SLT0 is used for RTEMS clock, SLT1 is used for diagnostic pupose)
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RESOLUTION: System tick 10 millieconds (via SLT0)
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SERIAL PORTS: Internal PSC 0-3
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NETWORKING: Internal 10/100MHz FEC on two channels
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DRIVER INFORMATION
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==================
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CLOCK DRIVER: SLT0
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TIMER DRIVER: SLT1 (diagnostics)
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TTY DRIVER: PSC0-3
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STDIO
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=====
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PORT: PSC0 (UART mode) terminal
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ELECTRICAL: RS-232
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BAUD: 9600
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BITS PER CHARACTER: 8
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PARITY: None
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STOP BITS: 1
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MODES: Interrupt driven (polled mode alternatively)
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----------------------------------------------------------------------
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Memory map of m5484FireEngine as set up by BSP initialization:
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+--------------------------------------------------+
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0000 0000 | 64 MByte SDRAM (external) | 03FF FFFF
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. .
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. .
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. .
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m5484FireEngine:
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| | 0FFF FFFF
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+--------------------------------------------------+
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1000 0000 | internal per. registers via MBAR | 1003 FFFF
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. .
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. .
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. .
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+--------------------------------------------------+
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2000 0000 | 8K core SRAM (internal) | 2000 1FFF
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. .
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. .
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. .
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m5484FireEngine:
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+--------------------------------------------------+
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E000 0000 | 16M code flash (external) | E0FF FFFF
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. .
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. .
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. .
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+--------------------------------------------------+
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FF80 0000 | External 8 MByte Flash memory | FF9F FFFF
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. .
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. .
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. .
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| | FFFF FFFF
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+--------------------------------------------------+
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----------------------------------------------------------------------
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Memory map for COBRA5475 as set up by DBug:
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+--------------------------------------------------+
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F000 0000 | 128 MByte SDRAM (external) |
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. .
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. (first 256KByte reserved for DBug) .
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. . F03F FFFF
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F040 0000 | |
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. .
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. .
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. .
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| | F7FF FFFF
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+--------------------------------------------------+
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FC00 0000 | 32M code flash (external) |
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. .
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. .
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. .
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| | FDFF FFFF
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+--------------------------------------------------+
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FE00 0000 | internal per. registers via MBAR |
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. .
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. .
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. .
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| | FE03 FFFF
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+--------------------------------------------------+
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FF00 0000 | 8K core SRAM (internal) |
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. .
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. .
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. .
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| | FF00 1FFF
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+--------------------------------------------------+
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============================================================================
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Interrupt map
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+-----+-----------------------------------------------------------------------+
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| | PRIORITY |
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+-----+--------+--------+--------+--------+--------+--------+--------+--------+
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|LEVEL| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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+-----+--------+--------+--------+--------+--------+--------+--------+--------+
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| 7 | | | | | | | | |
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+-----+--------+--------+--------+--------+--------+--------+--------+--------+
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| 6 | | | | | | | | |
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+-----+--------+--------+--------+--------+--------+--------+--------+--------+
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| 5 | | | | | | | | |
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+-----+--------+--------+--------+--------+--------+--------+--------+--------+
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| 4 | | | | | | | | SLT0 |
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+-----+--------+--------+--------+--------+--------+--------+--------+--------+
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| 3 | PSC 0 | PSC 1 | PSC 2 | PSC 3 | | | | |
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+-----+--------+--------+--------+--------+--------+--------+--------+--------+
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| 2 | | | | | FEC0/1 | MCDMA | | |
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+-----+--------+--------+--------+--------+--------+--------+--------+--------+
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| 1 | | | | | | | | |
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+-----+--------+--------+--------+--------+--------+--------+--------+--------+
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============================================================================
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TIMING TESTS
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**************************
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tbd.
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