forked from Imagelibrary/rtems
518 lines
8.7 KiB
Plaintext
518 lines
8.7 KiB
Plaintext
; /* @(#)amd.ah 1.1 96/05/23 08:56:58, TEI */
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; Initialization values for registers after RESET
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; /* $Id$ */
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;
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;* File information and includes.
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.file "amd.ah"
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.ident "@(#)amd.ah 1.1 96/05/23 08:56:58, TEI"
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;
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;* AMD PROCESSOR SPECIFIC VALUES...
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;
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;
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;* Processor revision levels...
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;
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; PRL values: 31-28 27-24
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; Am29000 0 x
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; Am29005 1 x
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; Am29050 2 x
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; Am29035 3 x
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; Am29030 4 x
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; Am29200 5 x
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; Am29205 5 1x
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; Am29240 6 0
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; Manx 7 0
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; Cougar 8 0
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.equ AM29000_PRL, 0x00
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.equ AM29005_PRL, 0x10
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.equ AM29050_PRL, 0x20
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.equ AM29035_PRL, 0x30
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.equ AM29030_PRL, 0x40
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.equ AM29200_PRL, 0x50
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.equ AM29205_PRL, 0x58
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.equ AM29240_PRL, 0x60
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.equ AM29040_PRL, 0x70
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.equ MANX_PRL, 0x70
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.equ COUGAR_PRL, 0x80
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;
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;* data structures sizes.
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;
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.equ CFGINFO_SIZE, 16*4
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.equ PGMINFO_SIZE, 16*4
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.equ VARARGS_SPACE, 16*4
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.equ WINDOWSIZE, 0x80
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;
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;* Am29027 Mode registers
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;
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.equ Am29027Mode1, 0x0fc00820
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.equ Am29027Mode2, 0x00001375
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;* Processor Based Equates and Defines
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.equ SIG_SYNC, -1
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.equ ENABLE, (SM)
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.equ DISABLE, (ENABLE | DI | DA)
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.equ DISABLE_FZ, (FZ | ENABLE | DI | DA)
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.equ CLR_TRAP, (FZ | DA)
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.equ InitOPS, (TD | SM | (3<<IMShift) | DI | DA)
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.equ InitCPS, (TD | SM | (0<<IMShift) | DI | DA)
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.equ InitCPS1, (TD | SM | (0<<IMShift) | DI )
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.equ CPS_TMR, (SM | (0<<IMShift) | DI)
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.equ CPS_INT0, (TD | SM | (0<<IMShift))
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.equ CPS_TMRINT0, (SM | (0<<IMShift))
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.equ InitCFG, 0x0
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.equ InitRBP, (B0|B1|B2|B3|B4|B5)
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.equ TMC_VALUE, 0xFFFFFF
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.equ TMR_VALUE, (IE | TMC_VALUE)
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;* 29205 specific (internal) peripheral initialization constants.
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; Current Processor Status (CPS) Register.
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; Old Processor Status Register (OPS).
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.equ DA, 0x00001
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.equ DI, 0x00002
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.equ IMShift,0x2
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.equ SM, 0x00010
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.equ PI, 0x00020
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.equ PD, 0x00040
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.equ WM, 0x00080
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.equ RE, 0x00100
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.equ LK, 0x00200
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.equ FZ, 0x00400
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.equ TU, 0x00800
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.equ TP, 0x01000
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.equ TE, 0x02000
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.equ IP, 0x04000
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.equ CA, 0x08000
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.equ MM, 0x10000
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.equ TD, 0x20000
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; Configuration Register (CFG)
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.equ CD, 0x01
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.equ CP, 0x02
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.equ BO, 0x04
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.equ RV, 0x08
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.equ VF, 0x10
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.equ DW, 0x20
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.equ CO, 0x40
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.equ EE, 0x80
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.equ IDShift, 8
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.equ CFG_ID, 0x100
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.equ ILShift, 9
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.equ CFG_ILMask, 0x600
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.equ DDShift, 11
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.equ CFG_DD, 0x800
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.equ DLShift, 12
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.equ CFG_DLMask, 0x3000
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.equ PCEShift, 14
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.equ CFG_PCE, 0x4000
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.equ PMBShift, 16
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.equ D16, 0x8000
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.equ TBOShift, 23
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.equ PRLShift, 24
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; Channel Control Register (CHC)
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.equ CV, 0x1
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.equ NN, 0x2
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.equ TRShift, 2
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.equ TF, 0x400
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.equ PER, 0x800
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.equ LA, 0x1000
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.equ ST, 0x2000
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.equ ML, 0x4000
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.equ LS, 0x8000
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.equ CRShift, 16
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.equ CNTLShift, 24
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.equ CEShift, 31
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.equ WBERShift, 31
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; Register Bank Protect (RBP)
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.equ B0, 0x1
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.equ B1, 0x2
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.equ B2, 0x4
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.equ B3, 0x8
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.equ B4, 0x10
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.equ B5, 0x20
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.equ B6, 0x40
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.equ B7, 0x80
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.equ B8, 0x100
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.equ B9, 0x200
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.equ B10, 0x400
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.equ B11, 0x800
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.equ B12, 0x1000
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.equ B13, 0x2000
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.equ B14, 0x4000
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.equ B15, 0x8000
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; Timer Counter
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.equ TCVMask, 0xffffff
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; Timer Reload Register
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.equ IE, 0x1000000
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.equ IN, 0x2000000
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.equ OV, 0x4000000
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.equ TRVMAsk, 0xffffff
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; MMU Configuration
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.equ PSShift, 8
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.equ PS0Shift, 8
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.equ PS1Shift, 12
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; LRU Recommendation (LRU)
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.equ LRUMask, 0xff
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; Reason Vector (RSN)
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.equ RSNMask, 0xff
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; Region Mapping Address (RMA0 | RMA1)
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.equ PBAMask,0xffff
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.equ VBAShift, 16
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; Region Mapping Control (RMC0 | RMC1)
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.equ TIDMask, 0xff
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.equ RMC_UE, 0x100
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.equ RMC_UW, 0x200
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.equ RMC_UR, 0x400
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.equ RMC_SE, 0x800
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.equ RMC_SW, 0x1000
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.equ RMC_SR, 0x2000
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.equ RMC_VE, 0x4000
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.equ RMC_IO, 0x10000
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.equ RGSShift, 17
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.equ RMC_PGMShift, 22
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; Instruction breakpoint Control (IBC0 | IBC1)
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.equ BPIDMask, 0xff
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.equ BTE, 0x100
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.equ BRM, 0x200
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.equ IBC_BSY, 0x400
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.equ BEN, 0x800
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.equ BHO, 0x1000
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; Cache Data Register (CDR)
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.equ CDR_US, 0x1
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.equ P, 0x2
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.equ CDR_V, 0x4
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.equ IATAGShift, 20
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; Cache Interface Register (CIR)
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.equ CPTRShift, 2
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.equ CIR_RW, 0x1000000
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.equ FSELShift, 28
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; Indirect Pointer A, B, C (IPA, IPB, IPC)
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.equ IPShift, 2
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; ALU Status (ALU)
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.equ FCMask, 0x1F
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.equ BPShift, 5
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.equ C, 0x80
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.equ Z, 0x100
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.equ N, 0x200
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.equ ALU_V, 0x400
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.equ DF, 0x800
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; Byte Pointer
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.equ BPMask, 0x3
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; Load/Store Count Remaining (CR)
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.equ CRMask, 0xff
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; Floating Point Environment (FPE)
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.equ NM, 0x1
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.equ RM, 0x2
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.equ VM, 0x4
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.equ UM, 0x8
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.equ XM, 0x10
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.equ DM, 0x20
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.equ FRMShift, 6
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.equ FF, 0x100
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.equ ACFShift, 9
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; Integer Environment (INTE)
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.equ MO, 0x1
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.equ DO, 0x2
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; Floating Point Status (FPS)
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.equ NS, 0x1
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.equ RS, 0x2
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.equ VS, 0x4
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.equ FPS_US, 0x8
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.equ XS, 0x10
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.equ DS, 0x20
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.equ NT, 0x100
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.equ RT, 0x200
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.equ VT, 0x400
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.equ UT, 0x800
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.equ XT, 0x1000
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.equ DT, 0x2000
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; Exception Opcode (EXOP)
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.equ IOPMask, 0xff
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; TLB Entry Word 0
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; .equ TIDMask, 0xff already defined above
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.equ TLB_UE, 0x100
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.equ TLB_UW, 0x200
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.equ TLB_UR, 0x400
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.equ TLB_SE, 0x800
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.equ TLB_SW, 0x1000
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.equ TLB_SR, 0x2000
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.equ TLB_VE, 0x4000
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.equ VTAGShift, 15
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; TLB Entry Word 1
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.equ TLB_IO, 0x1
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.equ U, 0x2
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.equ TLB_PGMShift, 6
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.equ RPNShift, 10
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; Am29200 ROM Control bits.
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.equ RMCT_DW0Shift, 29
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.equ RMCT_DW1Shift, 21
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.equ RMCT_DW2Shift, 13
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.equ RMCT_DW3Shift, 5
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; Am29200 DRAM Control bits.
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.equ DW3, (1<<18)
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.equ DW2, (1<<22)
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.equ DW1, (1<<26)
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.equ DW0, (1<<30)
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; Internal peripheral address assignments.
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.equ RMCT, 0x80000000
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.equ RMCF, 0x80000004
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.equ DRCT, 0x80000008
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.equ DRCF, 0x8000000C
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.equ DRM0, 0x80000010
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.equ DRM1, 0x80000014
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.equ DRM2, 0x80000018
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.equ DRM3, 0x8000001C
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.equ PIACT0, 0x80000020
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.equ PIACT1, 0x80000020
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.equ ICT, 0x80000028
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.equ DMCT0, 0x80000030
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.equ DMAD0, 0x80000034
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.ifdef revA
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.equ TAD0, 0x80000036
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.equ TCN0, 0x8000003A
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.else
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.equ TAD0, 0x80000070 ; default
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.equ TCN0, 0x8000003C ; default
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.endif
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.equ DMCN0, 0x80000038
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.equ DMCT1, 0x80000040
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.equ DMAD1, 0x80000044
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.equ DMCN1, 0x80000048
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.equ SPCT, 0x80000080
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.equ SPST, 0x80000084
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.equ SPTH, 0x80000088
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.equ SPRB, 0x8000008C
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.equ BAUD, 0x80000090
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.equ PPCT, 0x800000C0
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.equ PPST, 0x800000C1
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.equ PPDT, 0x800000C4
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.equ POCT, 0x800000D0
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.equ PIN, 0x800000D4
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.equ POUT, 0x800000D8
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.equ POEN, 0x800000DC
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.equ VCT, 0x800000E0
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.equ TOP, 0x800000E4
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.equ SIDE, 0x800000E8
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.equ VDT, 0x800000EC
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; Interrupt Controller Register bits.
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.equ TXDI, (1<<5)
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.equ RXDI, (1<<6)
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.equ RXSI, (1<<7)
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.equ PPI, (1<<11)
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.equ DMA1I, (1<<13)
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.equ DMA0I, (1<<14)
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.equ IOPIMask, (0xFF<<16)
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.equ VDI, (1<<27)
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.equ ICT200_I, (TXDI|RXDI|RXSI|PPI|DMA1I|DMA0I|IOPIMask|VDI)
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.equ ICT205_I, (TXDI|RXDI|RXSI|PPI|DMA1I|DMA0I|IOPIMask|VDI)
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; Serial port Initialization bits
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.equ NO_PARITY, 0
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; SPST bits
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.equ THREShift, 22
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;* REGISTER Addresses
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.equ ROMCntlRegAddr, 0x80000000
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.equ ROMCfgRegAddr, 0x80000004
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.equ DRAMCntlRegAddr, 0x80000008
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.equ DRAMCfgRegAddr, 0x8000000C
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.equ DRAMMap0RegAddr, 0x80000010
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.equ DRAMMap1RegAddr, 0x80000014
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.equ DRAMMap2RegAddr, 0x80000018
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.equ DRAMMap3RegAddr, 0x8000001C
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.equ PIACntl0RegAddr, 0x80000020
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.equ PIACntl1RegAddr, 0x80000024
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.equ INTRCntlRegAddr, 0x80000028
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.equ DMACntl0RegAddr, 0x80000030
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.equ DMACntl1RegAddr, 0x80000040
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.equ SERPortCntlRegAddr, 0x80000080
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.equ SERPortStatRegAddr, 0x80000084
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.equ SERPortTHLDRegAddr, 0x80000088
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.equ SERPortRbufRegAddr, 0x8000008C
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.equ SERPortBaudRegAddr, 0x80000090
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.equ PARPortCntlRegAddr, 0x800000C0
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.equ PIOCntlRegAddr, 0x800000D0
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.equ PIOInpRegAddr, 0x800000D4
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.equ PIOOutRegAddr, 0x800000D8
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.equ PIOOutEnaRegAddr, 0x800000DC
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.equ VCTCntlRegAddr, 0x800000E0
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;
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;* Control constants
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;
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;* AM29030 Timer related constants.
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.equ TMR_IE, 0x01000000
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.equ TMR_IN, 0x02000000
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.equ TMR_OV, 0x04000000
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.equ TMC_INITCNT, 1613
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;
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;* System initialization values.
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;
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.equ __os_version, 0x0001 ;
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.equ STACKSize, 0x8000 ;
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.equ PGMExecMode, 0x0000 ;
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.equ TSTCK_OFST, 28 * 4
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.equ CSTCK_OFST, 29 * 4
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.equ TMSTCK_OFST, 30 * 4
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.equ CMSTCK_OFST, 31 * 4
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.equ CTXSW_OK, 0xA55A ; ctx switch ok
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.set NV_STARTOFST, 0x20 ; 32 bytes
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.set NV_BAUDOFST, 0x00 ; 00 bytes
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.set reg_cir, 29
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.set reg_cdr, 30
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.equ MSG_BUFSIZE, 0x1000 ; serial buffer size
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.equ ILLOPTRAP, 0
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.equ UATRAP, 1
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.equ PVTRAP, 5
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.equ UITLBMISSTRAP, 8
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.equ UDTLBMISSTRAP, 9
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.equ TIMERTRAP, 14
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.equ TRACETRAP, 15
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.equ XLINXTRAP, 16
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.equ SERIALTRAP, 17
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.equ SLOWTMRTRAP, 18
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.equ PORTTRAP, 19
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.equ SVSCTRAP, 80
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.equ SVSCTRAP1, 81
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.equ V_CACHETRAP, 66 ;
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.equ V_SETSERVICE, 67 ;
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