forked from Imagelibrary/rtems
d19cce29dc
Use a per-CPU thread dispatch disable level. So instead of one global thread dispatch disable level we have now one instance per processor. This is a major performance improvement for SMP. On non-SMP configurations this may simplifiy the interrupt entry/exit code. The giant lock is still present, but it is now decoupled from the thread dispatching in _Thread_Dispatch(), _Thread_Handler(), _Thread_Restart_self() and the interrupt entry/exit. Access to the giant lock is now available via _Giant_Acquire() and _Giant_Release(). The giant lock is still implicitly acquired via _Thread_Dispatch_decrement_disable_level(). The giant lock is only acquired for high-level operations in interrupt handlers (e.g. release of a semaphore, sending of an event). As a side-effect this change fixes the lost thread dispatch necessary indication bug in _Thread_Dispatch(). A per-CPU thread dispatch disable level greatly simplifies the SMP support for the interrupt entry/exit code since no spin locks have to be acquired in this area. It is only necessary to get the current processor index and use this to calculate the address of the own per-CPU control. This reduces the interrupt latency considerably. All elements for the interrupt entry/exit code are now part of the Per_CPU_Control structure: thread dispatch disable level, ISR nest level and thread dispatch necessary. Nothing else is required (except CPU port specific stuff like on SPARC).
179 lines
5.1 KiB
C
179 lines
5.1 KiB
C
/**
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* @file
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*
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* @brief Dispatch Thread
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* @ingroup ScoreThread
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*/
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/*
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* COPYRIGHT (c) 1989-2009.
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* On-Line Applications Research Corporation (OAR).
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.com/license/LICENSE.
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*/
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#if HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include <rtems/score/threaddispatch.h>
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#include <rtems/score/apiext.h>
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#include <rtems/score/assert.h>
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#include <rtems/score/isr.h>
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#include <rtems/score/threadimpl.h>
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#include <rtems/score/todimpl.h>
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#include <rtems/score/userextimpl.h>
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#include <rtems/score/wkspace.h>
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void _Thread_Dispatch( void )
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{
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Per_CPU_Control *per_cpu;
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Thread_Control *executing;
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Thread_Control *heir;
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ISR_Level level;
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#if defined( RTEMS_SMP )
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_ISR_Disable( level );
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#endif
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per_cpu = _Per_CPU_Get();
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_Assert( per_cpu->thread_dispatch_disable_level == 0 );
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per_cpu->thread_dispatch_disable_level = 1;
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#if defined( RTEMS_SMP )
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_ISR_Enable( level );
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#endif
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/*
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* Now determine if we need to perform a dispatch on the current CPU.
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*/
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executing = per_cpu->executing;
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_Per_CPU_ISR_disable_and_acquire( per_cpu, level );
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#if defined( RTEMS_SMP )
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/*
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* On SMP the complete context switch must be atomic with respect to one
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* processor. The scheduler must obtain the per-CPU lock to check if a
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* thread is executing and to update the heir. This ensures that a thread
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* cannot execute on more than one processor at a time. See also
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* _Thread_Handler() since _Context_switch() may branch to this function.
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*/
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if ( per_cpu->dispatch_necessary ) {
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#else
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while ( per_cpu->dispatch_necessary ) {
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#endif
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heir = per_cpu->heir;
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per_cpu->dispatch_necessary = false;
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per_cpu->executing = heir;
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#if defined( RTEMS_SMP )
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executing->is_executing = false;
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heir->is_executing = true;
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#endif
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/*
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* When the heir and executing are the same, then we are being
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* requested to do the post switch dispatching. This is normally
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* done to dispatch signals.
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*/
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if ( heir == executing )
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goto post_switch;
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/*
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* Since heir and executing are not the same, we need to do a real
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* context switch.
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*/
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#if __RTEMS_ADA__
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executing->rtems_ada_self = rtems_ada_self;
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rtems_ada_self = heir->rtems_ada_self;
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#endif
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if ( heir->budget_algorithm == THREAD_CPU_BUDGET_ALGORITHM_RESET_TIMESLICE )
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heir->cpu_time_budget = _Thread_Ticks_per_timeslice;
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#if !defined( RTEMS_SMP )
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_ISR_Enable( level );
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#endif
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#ifndef __RTEMS_USE_TICKS_FOR_STATISTICS__
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_Thread_Update_cpu_time_used(
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executing,
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&per_cpu->time_of_last_context_switch
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);
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#else
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{
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_TOD_Get_uptime( &per_cpu->time_of_last_context_switch );
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heir->cpu_time_used++;
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}
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#endif
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#if !defined(__DYNAMIC_REENT__)
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/*
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* Switch libc's task specific data.
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*/
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if ( _Thread_libc_reent ) {
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executing->libc_reent = *_Thread_libc_reent;
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*_Thread_libc_reent = heir->libc_reent;
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}
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#endif
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_User_extensions_Thread_switch( executing, heir );
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/*
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* If the CPU has hardware floating point, then we must address saving
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* and restoring it as part of the context switch.
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*
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* The second conditional compilation section selects the algorithm used
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* to context switch between floating point tasks. The deferred algorithm
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* can be significantly better in a system with few floating point tasks
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* because it reduces the total number of save and restore FP context
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* operations. However, this algorithm can not be used on all CPUs due
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* to unpredictable use of FP registers by some compilers for integer
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* operations.
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*/
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#if ( CPU_HARDWARE_FP == TRUE ) || ( CPU_SOFTWARE_FP == TRUE )
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#if ( CPU_USE_DEFERRED_FP_SWITCH != TRUE )
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if ( executing->fp_context != NULL )
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_Context_Save_fp( &executing->fp_context );
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#endif
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#endif
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_Context_Switch( &executing->Registers, &heir->Registers );
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#if ( CPU_HARDWARE_FP == TRUE ) || ( CPU_SOFTWARE_FP == TRUE )
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#if ( CPU_USE_DEFERRED_FP_SWITCH == TRUE )
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if ( (executing->fp_context != NULL) &&
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!_Thread_Is_allocated_fp( executing ) ) {
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if ( _Thread_Allocated_fp != NULL )
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_Context_Save_fp( &_Thread_Allocated_fp->fp_context );
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_Context_Restore_fp( &executing->fp_context );
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_Thread_Allocated_fp = executing;
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}
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#else
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if ( executing->fp_context != NULL )
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_Context_Restore_fp( &executing->fp_context );
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#endif
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#endif
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/*
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* We have to obtain these values again after the context switch since the
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* heir thread may have migrated from another processor. Values from the
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* stack or non-volatile registers reflect the old execution environment.
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*/
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per_cpu = _Per_CPU_Get();
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executing = per_cpu->executing;
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#if !defined( RTEMS_SMP )
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_ISR_Disable( level );
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#endif
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}
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post_switch:
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_Assert( per_cpu->thread_dispatch_disable_level == 1 );
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per_cpu->thread_dispatch_disable_level = 0;
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_Per_CPU_Release_and_ISR_enable( per_cpu, level );
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_API_extensions_Run_post_switch( executing );
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}
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