forked from Imagelibrary/rtems
d19cce29dc
Use a per-CPU thread dispatch disable level. So instead of one global thread dispatch disable level we have now one instance per processor. This is a major performance improvement for SMP. On non-SMP configurations this may simplifiy the interrupt entry/exit code. The giant lock is still present, but it is now decoupled from the thread dispatching in _Thread_Dispatch(), _Thread_Handler(), _Thread_Restart_self() and the interrupt entry/exit. Access to the giant lock is now available via _Giant_Acquire() and _Giant_Release(). The giant lock is still implicitly acquired via _Thread_Dispatch_decrement_disable_level(). The giant lock is only acquired for high-level operations in interrupt handlers (e.g. release of a semaphore, sending of an event). As a side-effect this change fixes the lost thread dispatch necessary indication bug in _Thread_Dispatch(). A per-CPU thread dispatch disable level greatly simplifies the SMP support for the interrupt entry/exit code since no spin locks have to be acquired in this area. It is only necessary to get the current processor index and use this to calculate the address of the own per-CPU control. This reduces the interrupt latency considerably. All elements for the interrupt entry/exit code are now part of the Per_CPU_Control structure: thread dispatch disable level, ISR nest level and thread dispatch necessary. Nothing else is required (except CPU port specific stuff like on SPARC).
383 lines
13 KiB
ArmAsm
383 lines
13 KiB
ArmAsm
/* cpu_asm.s
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*
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* This file contains all assembly code for the MC68020 implementation
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* of RTEMS.
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*
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* COPYRIGHT (c) 1989-2008.
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* On-Line Applications Research Corporation (OAR).
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.com/license/LICENSE.
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*/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include <rtems/asm.h>
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#include <rtems/score/percpu.h>
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/* void _CPU_Context_switch( run_context, heir_context )
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*
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* This routine performs a normal non-FP context.
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*/
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.align 4
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.global SYM (_CPU_Context_switch)
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.set RUNCONTEXT_ARG, 4 | save context argument
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.set HEIRCONTEXT_ARG, 8 | restore context argument
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SYM (_CPU_Context_switch):
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moval a7@(RUNCONTEXT_ARG),a0| a0 = running thread context
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movw sr,d1 | d1 = status register
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movml d1-d7/a2-a7,a0@ | save context
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moval a7@(HEIRCONTEXT_ARG),a0| a0 = heir thread context
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#if defined( __mcoldfire__ ) && ( M68K_HAS_FPU == 1 )
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moveb a0@(13*4),d0 | get context specific DF bit info in d0
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btstb #4,d0 | test context specific DF bit info
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beq fpu_on | branch if FPU needs to be switched on
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fpu_off: movl _CPU_cacr_shadow,d0 | get content of _CPU_cacr_shadow in d0
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btstl #4,d0 | test DF bit info in d0
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bne restore | branch if FPU is already switched off
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bsetl #4,d0 | set DF bit in d0
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bra cacr_set | branch to set the new FPU setting in cacr and _CPU_cacr_shadow
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fpu_on: movl _CPU_cacr_shadow,d0 | get content of _CPU_cacr_shadow in d1
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btstl #4,d0 | test context specific DF bit info
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beq restore | branch if FPU is already switched on
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bclrl #4,d0 | clear DF bit info in d0
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cacr_set: movew sr,d1 | get content of sr in d1
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oril #0x00000700,d1 | mask d1
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movew d1,sr | disable all interrupts
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movl d0,_CPU_cacr_shadow | move _CPU_cacr_shadow to d1
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movec d0,cacr | enable FPU in cacr
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#endif
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restore: movml a0@,d1-d7/a2-a7 | restore context
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movw d1,sr | restore status register
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rts
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.global SYM (_CPU_Context_Restart_self)
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.set CONTEXT_ARG, 4 | context arg
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#if defined( __mcoldfire__ ) && ( M68K_HAS_FPU == 1 )
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/* XXX _CPU_Context_switch maintains FPU context -- do we have to restore
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* that, too??
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*/
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#warning "_CPU_Context_Restart_self restoring FPU context not implemented"
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#endif
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SYM(_CPU_Context_Restart_self):
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moval a7@(CONTEXT_ARG),a0
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bra restore
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/*
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* Floating point context save and restore.
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*
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* The code for the MC68881 or MC68882 is based upon the code shown on pages
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* 6-38 of the MC68881/68882 Users Manual (rev 1). CPU_FP_CONTEXT_SIZE is
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* higher than expected to account for the -1 pushed at end of this sequence.
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*/
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#if ( CPU_HARDWARE_FP == TRUE )
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.set FPCONTEXT_ARG, 4 | save FP context argument
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.align 4
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.global SYM (_CPU_Context_save_fp)
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SYM (_CPU_Context_save_fp):
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/* Get context save area pointer argument from the stack */
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moval a7@(FPCONTEXT_ARG), a1
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moval a1@, a0
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#if defined( __mcoldfire__ )
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/* Move MACSR to data register and disable rounding */
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movel macsr, d0
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clrl d1
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movl d1, macsr
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/* Save MACSR and ACC0 */
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movl acc0, d1
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moveml d0-d1, a0@(0)
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/* Save ACC1 and ACC2 */
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movl acc1, d0
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movl acc2, d1
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moveml d0-d1, a0@(8)
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/* Save ACC3 and ACCEXT01 */
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movl acc3, d0
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movl accext01, d1
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moveml d0-d1, a0@(16)
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/* Save ACCEXT23 and MASK */
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movl accext23, d0
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movl mask, d1
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moveml d0-d1, a0@(24)
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#if ( M68K_HAS_FPU == 1 )
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/* Save FP state */
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fsave a0@(32)
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/* Save FP instruction address */
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fmovel fpi, a0@(48)
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/* Save FP data */
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fmovem fp0-fp7, a0@(52)
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#endif
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#else
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#if defined( __mc68060__ )
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lea a0@(-M68K_FP_STATE_SIZE), a0
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fsave a0@ | save 68060 state frame
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#else
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fsave a0@- | save 68881/68882 state frame
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#endif
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tstb a0@ | check for a null frame
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beq.b nosv | Yes, skip save of user model
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fmovem fp0-fp7, a0@- | save data registers (fp0-fp7)
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fmovem fpc/fps/fpi, a0@- | and save control registers
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movl #-1, a0@- | place not-null flag on stack
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nosv:
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movl a0, a1@ | save pointer to saved context
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#endif
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/* Return */
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rts
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.align 4
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.global SYM (_CPU_Context_restore_fp)
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SYM (_CPU_Context_restore_fp):
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/* Get context save area pointer argument from the stack */
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moval a7@(FPCONTEXT_ARG), a1
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moval a1@, a0
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#if defined( __mcoldfire__ )
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#if ( M68K_HAS_FPU == 1 )
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/* Restore FP data */
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fmovem a0@(52), fp0-fp7
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/* Restore FP instruction address */
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fmovel a0@(48), fpi
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/* Restore FP state */
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frestore a0@(32)
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#endif
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/* Disable rounding */
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clrl d0
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movl d0, macsr
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/* Restore MASK and ACCEXT23 */
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moveml a0@(24), d0-d1
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movl d0, mask
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movl d1, accext23
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/* Restore ACCEXT01 and ACC3 */
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moveml a0@(16), d0-d1
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movl d0, accext01
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movl d1, acc3
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/* Restore ACC2 and ACC1 */
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moveml a0@(8), d0-d1
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movl d0, acc2
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movl d1, acc1
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/* Restore ACC0 and MACSR */
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moveml a0@(0), d0-d1
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movl d0, acc0
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movl d1, macsr
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#else
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tstb a0@ | Null context frame?
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beq.b norst | Yes, skip fp restore
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addql #4, a0 | throwaway non-null flag
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fmovem a0@+, fpc/fps/fpi | restore control registers
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fmovem a0@+, fp0-fp7 | restore data regs (fp0-fp7)
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norst:
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#if defined( __mc68060__ )
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frestore a0@ | restore 68060 state frame
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lea a0@(M68K_FP_STATE_SIZE), a0
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#else
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frestore a0@+ | restore 68881/68882 state frame
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#endif
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movl a0, a1@ | save pointer to saved context
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#endif
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/* Return */
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rts
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#endif
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/*void _ISR_Handler()
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*
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* This routine provides the RTEMS interrupt management.
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*
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* NOTE:
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* Upon entry, the master stack will contain an interrupt stack frame
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* back to the interrupted thread and the interrupt stack will contain
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* a throwaway interrupt stack frame. If dispatching is enabled, and this
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* is the outer most interrupt, and a context switch is necessary or
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* the current thread has pending signals, then set up the master stack to
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* transfer control to the interrupt dispatcher.
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*/
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#if ( defined(__mcoldfire__) )
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.set SR_OFFSET, 2 | Status register offset
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.set PC_OFFSET, 4 | Program Counter offset
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.set FVO_OFFSET, 0 | Format/vector offset
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#elif ( M68K_HAS_VBR == 1)
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.set SR_OFFSET, 0 | Status register offset
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.set PC_OFFSET, 2 | Program Counter offset
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.set FVO_OFFSET, 6 | Format/vector offset
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#else
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.set SR_OFFSET, 2 | Status register offset
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.set PC_OFFSET, 4 | Program Counter offset
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.set FVO_OFFSET, 0 | Format/vector offset placed in the stack
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#endif /* M68K_HAS_VBR */
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.set SAVED, 16 | space for saved registers
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.align 4
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.global SYM (_ISR_Handler)
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SYM (_ISR_Handler):
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| disable multitasking
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addql #1,THREAD_DISPATCH_DISABLE_LEVEL
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#if ( !defined(__mcoldfire__) )
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moveml d0-d1/a0-a1,a7@- | save d0-d1,a0-a1
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#else
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lea a7@(-SAVED),a7
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movm.l d0-d1/a0-a1,a7@ | save d0-d1,a0-a1
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#endif
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movew a7@(SAVED+FVO_OFFSET),d0 | d0 = F/VO
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andl #0x03fc,d0 | d0 = vector offset in vbr
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#if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 )
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| Make a0 point just above interrupt stack
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movel INTERRUPT_STACK_HIGH,a0
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cmpl INTERRUPT_STACK_LOW,a7 | stack below interrupt stack?
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bcs.b 1f | yes, switch to interrupt stack
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cmpl a0,a7 | stack above interrupt stack?
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bcs.b 2f | no, do not switch stacks
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1:
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movel a7,a1 | copy task stack pointer
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movel a0,a7 | switch to interrupt stack
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movel a1,a7@- | store task stack pointer
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| on interrupt stack
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2:
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#endif /* CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 */
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addql #1,ISR_NEST_LEVEL | one nest level deeper
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movel SYM (_ISR_Vector_table),a0 | a0= base of RTEMS table
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#if ( M68K_HAS_PREINDEXING == 1 )
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movel (a0,d0:w:1),a0 | a0 = address of user routine
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#else
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addal d0,a0 | a0 = address of vector
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movel (a0),a0 | a0 = address of user routine
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#endif
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lsrl #2,d0 | d0 = vector number
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movel d0,a7@- | push vector number
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jbsr a0@ | invoke the user ISR
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addql #4,a7 | remove vector number
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subql #1,ISR_NEST_LEVEL | Reduce interrupt-nesting count
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#if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 )
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movel INTERRUPT_STACK_HIGH,a0
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subql #4,a0
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cmpl a0,a7 | At top of interrupt stack?
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bne.b 1f | No, do not restore task stack pointer
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movel (a7),a7 | Restore task stack pointer
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1:
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#endif /* CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 */
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subql #1,THREAD_DISPATCH_DISABLE_LEVEL
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| unnest multitasking
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bne.b exit | If dispatch disabled, exit
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#if ( M68K_HAS_SEPARATE_STACKS == 1 )
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movew #0xf000,d0 | isolate format nibble
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andw a7@(SAVED+FVO_OFFSET),d0 | get F/VO
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cmpiw #0x1000,d0 | is it a throwaway isf?
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bne.b exit | NOT outer level, so branch
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#else
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/*
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* If we have a CPU which allows a higher-priority interrupt to preempt a
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* lower priority handler before the lower-priority handler can increment
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* _Thread_Dispatch_disable_level then we must check the PC on the stack to
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* see if it is _ISR_Handler. If it is we have the case of nesting interrupts
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* without the dispatch level being incremented.
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*/
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#if ( !defined(__mcoldfire__) && !__mc68060__ )
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cmpl #_ISR_Handler,a7@(SAVED+PC_OFFSET)
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beq.b exit
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#endif
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#endif
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tstb DISPATCH_NEEDED
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| Is thread switch necessary?
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beq.b exit | No, then exit
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bframe:
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| If sent, will be processed
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#if ( M68K_HAS_SEPARATE_STACKS == 1 )
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movec msp,a0 | a0 = master stack pointer
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movew #0,a0@- | push format word
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movel #SYM(_ISR_Dispatch),a0@- | push return addr
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movew a0@(6),a0@- | push saved sr
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movec a0,msp | set master stack pointer
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#else
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jsr SYM (_Thread_Dispatch) | Perform context switch
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#endif
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#if ( !defined(__mcoldfire__) )
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exit: moveml a7@+,d0-d1/a0-a1 | restore d0-d1,a0-a1
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#else
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exit: moveml a7@,d0-d1/a0-a1 | restore d0-d1,a0-a1
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lea a7@(SAVED),a7
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#endif
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#if ( M68K_HAS_VBR == 0 )
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addql #2,a7 | pop format/id
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#endif /* M68K_HAS_VBR */
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rte | return to thread
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| OR _Isr_dispatch
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/*void _ISR_Dispatch()
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*
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* Entry point from the outermost interrupt service routine exit.
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* The current stack is the supervisor mode stack if this processor
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* has separate stacks.
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*
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* 1. save all registers not preserved across C calls.
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* 2. invoke the _Thread_Dispatch routine to switch tasks
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* or a signal to the currently executing task.
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* 3. restore all registers not preserved across C calls.
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* 4. return from interrupt
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*/
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.global SYM (_ISR_Dispatch)
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SYM (_ISR_Dispatch):
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#if ( !defined(__mcoldfire__) )
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movml d0-d1/a0-a1,a7@-
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jsr SYM (_Thread_Dispatch)
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movml a7@+,d0-d1/a0-a1
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#else
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lea a7@(-SAVED),a7
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movml d0-d1/a0-a1,a7@
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jsr SYM (_Thread_Dispatch)
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movml a7@,d0-d1/a0-a1
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lea a7@(SAVED),a7
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#endif
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#if ( M68K_HAS_VBR == 0 )
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addql #2,a7 | pop format/id
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#endif /* M68K_HAS_VBR */
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rte
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