forked from Imagelibrary/rtems
320 lines
6.8 KiB
C
320 lines
6.8 KiB
C
/**
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* @file
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*
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* #ingroup RTEMSBSPsPowerPCShared
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*
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* @brief Header file for the Cache Manager PowerPC support.
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*/
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/*
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* Cache Management Support Routines for the MC68040
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* Modified for MPC8260 Andy Dachs <a.dachs@sstl.co.uk>
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* Surrey Satellite Technology Limited (SSTL), 2001
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*/
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#include <rtems.h>
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#include <rtems/powerpc/powerpc.h>
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#include <rtems/powerpc/registers.h>
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/* Provide the CPU defines only if we have a cache */
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#if PPC_CACHE_ALIGNMENT != PPC_NO_CACHE_ALIGNMENT
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#define CPU_DATA_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT
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#define CPU_INSTRUCTION_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT
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#endif
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#define CPU_CACHE_SUPPORT_PROVIDES_CACHE_SIZE_FUNCTIONS
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static inline size_t _CPU_cache_get_data_cache_size(uint32_t level)
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{
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switch (level) {
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case 0:
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/* Fall through */
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#ifdef PPC_CACHE_DATA_L3_SIZE
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case 3:
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return PPC_CACHE_DATA_L3_SIZE;
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#endif
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#ifdef PPC_CACHE_DATA_L2_SIZE
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case 2:
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return PPC_CACHE_DATA_L2_SIZE;
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#endif
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#ifdef PPC_CACHE_DATA_L1_SIZE
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case 1:
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return PPC_CACHE_DATA_L1_SIZE;
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#endif
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default:
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return 0;
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}
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}
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static inline size_t _CPU_cache_get_instruction_cache_size(uint32_t level)
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{
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switch (level) {
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case 0:
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/* Fall through */
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#ifdef PPC_CACHE_INSTRUCTION_L3_SIZE
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case 3:
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return PPC_CACHE_INSTRUCTION_L3_SIZE;
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#endif
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#ifdef PPC_CACHE_INSTRUCTION_L2_SIZE
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case 2:
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return PPC_CACHE_INSTRUCTION_L2_SIZE;
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#endif
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#ifdef PPC_CACHE_INSTRUCTION_L1_SIZE
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case 1:
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return PPC_CACHE_INSTRUCTION_L1_SIZE;
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#endif
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default:
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return 0;
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}
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}
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/*
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* CACHE MANAGER: The following functions are CPU-specific.
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* They provide the basic implementation for the rtems_* cache
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* management routines. If a given function has no meaning for the CPU,
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* it does nothing by default.
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*
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* FIXME: Some functions simply have not been implemented.
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*/
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#if defined(ppc603) || defined(ppc603e) || defined(mpc8260) /* And possibly others */
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/* Helpful macros */
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#define PPC_Get_HID0( _value ) \
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do { \
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_value = 0; /* to avoid warnings */ \
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__asm__ volatile( \
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"mfspr %0, 0x3f0;" /* get HID0 */ \
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"isync" \
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: "=r" (_value) \
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: "0" (_value) \
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); \
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} while (0)
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#define PPC_Set_HID0( _value ) \
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do { \
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__asm__ volatile( \
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"isync;" \
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"mtspr 0x3f0, %0;" /* load HID0 */ \
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"isync" \
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: "=r" (_value) \
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: "0" (_value) \
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); \
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} while (0)
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static inline void _CPU_cache_enable_data(void)
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{
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uint32_t value;
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PPC_Get_HID0( value );
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value |= HID0_DCE; /* set DCE bit */
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PPC_Set_HID0( value );
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}
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static inline void _CPU_cache_disable_data(void)
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{
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uint32_t value;
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PPC_Get_HID0( value );
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value &= ~HID0_DCE; /* clear DCE bit */
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PPC_Set_HID0( value );
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}
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static inline void _CPU_cache_invalidate_entire_data(void)
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{
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uint32_t value;
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PPC_Get_HID0( value );
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value |= HID0_DCI; /* set data flash invalidate bit */
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PPC_Set_HID0( value );
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value &= ~HID0_DCI; /* clear data flash invalidate bit */
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PPC_Set_HID0( value );
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}
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static inline void _CPU_cache_freeze_data(void)
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{
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uint32_t value;
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PPC_Get_HID0( value );
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value |= HID0_DLOCK; /* set data cache lock bit */
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PPC_Set_HID0( value );
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}
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static inline void _CPU_cache_unfreeze_data(void)
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{
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uint32_t value;
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PPC_Get_HID0( value );
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value &= ~HID0_DLOCK; /* set data cache lock bit */
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PPC_Set_HID0( value );
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}
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static inline void _CPU_cache_flush_entire_data(void)
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{
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/*
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* FIXME: how can we do this?
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*/
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}
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static inline void _CPU_cache_enable_instruction(void)
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{
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uint32_t value;
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PPC_Get_HID0( value );
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value |= 0x00008000; /* Set ICE bit */
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PPC_Set_HID0( value );
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}
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static inline void _CPU_cache_disable_instruction(void)
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{
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uint32_t value;
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PPC_Get_HID0( value );
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value &= 0xFFFF7FFF; /* Clear ICE bit */
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PPC_Set_HID0( value );
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}
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static inline void _CPU_cache_invalidate_entire_instruction(void)
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{
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uint32_t value;
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PPC_Get_HID0( value );
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value |= HID0_ICFI; /* set data flash invalidate bit */
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PPC_Set_HID0( value );
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value &= ~HID0_ICFI; /* clear data flash invalidate bit */
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PPC_Set_HID0( value );
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}
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static inline void _CPU_cache_freeze_instruction(void)
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{
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uint32_t value;
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PPC_Get_HID0( value );
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value |= HID0_ILOCK; /* set instruction cache lock bit */
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PPC_Set_HID0( value );
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}
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static inline void _CPU_cache_unfreeze_instruction(void)
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{
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uint32_t value;
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PPC_Get_HID0( value );
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value &= ~HID0_ILOCK; /* set instruction cache lock bit */
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PPC_Set_HID0( value );
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}
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#elif ( defined(mpx8xx) || defined(mpc860) || defined(mpc821) )
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#define mtspr(_spr,_reg) \
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__asm__ volatile ( "mtspr %0, %1\n" : : "i" ((_spr)), "r" ((_reg)) )
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#define isync \
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__asm__ volatile ("isync\n"::)
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static inline void _CPU_cache_flush_entire_data(void) {}
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static inline void _CPU_cache_invalidate_entire_data(void) {}
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static inline void _CPU_cache_freeze_data(void) {}
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static inline void _CPU_cache_unfreeze_data(void) {}
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static inline void _CPU_cache_enable_data(void)
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{
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uint32_t r1;
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r1 = (0x2<<24);
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mtspr( 568, r1 );
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isync;
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}
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static inline void _CPU_cache_disable_data(void)
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{
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uint32_t r1;
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r1 = (0x4<<24);
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mtspr( 568, r1 );
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isync;
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}
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static inline void _CPU_cache_invalidate_entire_instruction(void) {}
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static inline void _CPU_cache_freeze_instruction(void) {}
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static inline void _CPU_cache_unfreeze_instruction(void) {}
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static inline void _CPU_cache_enable_instruction(void)
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{
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uint32_t r1;
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r1 = (0x2<<24);
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mtspr( 560, r1 );
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isync;
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}
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static inline void _CPU_cache_disable_instruction(void)
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{
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uint32_t r1;
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r1 = (0x4<<24);
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mtspr( 560, r1 );
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isync;
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}
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#else
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static inline void _CPU_cache_flush_entire_data(void)
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{
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/* Void */
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}
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static inline void _CPU_cache_invalidate_entire_data(void)
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{
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/* Void */
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}
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static inline void _CPU_cache_freeze_data(void)
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{
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/* Void */
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}
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static inline void _CPU_cache_unfreeze_data(void)
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{
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/* Void */
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}
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static inline void _CPU_cache_enable_data(void)
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{
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/* Void */
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}
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static inline void _CPU_cache_disable_data(void)
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{
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/* Void */
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}
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static inline void _CPU_cache_invalidate_entire_instruction(void)
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{
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/* Void */
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}
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static inline void _CPU_cache_freeze_instruction(void)
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{
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/* Void */
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}
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static inline void _CPU_cache_unfreeze_instruction(void)
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{
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/* Void */
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}
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static inline void _CPU_cache_enable_instruction(void)
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{
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/* Void */
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}
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static inline void _CPU_cache_disable_instruction(void)
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{
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/* Void */
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}
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#endif
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static inline void _CPU_cache_invalidate_1_data_line(const void *addr)
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{
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__asm__ volatile ( "dcbi 0,%0" :: "r" (addr) : "memory" );
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}
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static inline void _CPU_cache_flush_1_data_line(const void *addr)
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{
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__asm__ volatile ( "dcbf 0,%0" :: "r" (addr) : "memory" );
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}
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static inline void _CPU_cache_invalidate_1_instruction_line(const void *addr)
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{
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__asm__ volatile ( "icbi 0,%0" :: "r" (addr) : "memory");
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}
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#include "../../../bsps/shared/cache/cacheimpl.h"
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