forked from Imagelibrary/rtems
133 lines
2.4 KiB
C
133 lines
2.4 KiB
C
/**
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* @file
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*
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* @ingroup lpc_i2s
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*
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* @brief I2S API.
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*/
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/*
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* Copyright (c) 2010 embedded brains GmbH. All rights reserved.
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*
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* embedded brains GmbH
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* Obere Lagerstr. 30
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* 82178 Puchheim
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* Germany
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* <rtems@embedded-brains.de>
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#ifndef LIBBSP_ARM_SHARED_LPC_I2S_H
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#define LIBBSP_ARM_SHARED_LPC_I2S_H
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#include <bsp/utility.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @defgroup lpc_i2s I2S Support
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*
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* @ingroup RTEMSBSPsARMLPC24XX
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* @ingroup RTEMSBSPsARMLPC32XX
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*
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* @brief I2S support.
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*
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* @{
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*/
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/**
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* @brief I2S control block.
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*/
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typedef struct {
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uint32_t dao;
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uint32_t dai;
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uint32_t txfifo;
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uint32_t rxfifo;
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uint32_t state;
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uint32_t dma [2];
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uint32_t irq;
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uint32_t txrate;
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uint32_t rxrate;
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} lpc_i2s;
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/**
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* @name I2S Digital Audio Input and Output
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*
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* @{
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*/
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#define I2S_DAIO_WORDWIDTH(val) BSP_FLD32(val, 0, 1)
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#define I2S_DAIO_MONO BSP_BIT32(2)
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#define I2S_DAIO_STOP BSP_BIT32(3)
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#define I2S_DAIO_RESET BSP_BIT32(4)
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#define I2S_DAIO_WS_SEL BSP_BIT32(5)
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#define I2S_DAIO_WS_HALFPERIOD(val) BSP_FLD32(val, 6, 14)
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#define I2S_DAIO_MUTE BSP_BIT32(15)
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/** @} */
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/**
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* @name I2S Status Feedback
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*
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* @{
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*/
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#define I2S_STATE_IRQ BSP_BIT32(0)
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#define I2S_STATE_DMAREQ_0 BSP_BIT32(1)
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#define I2S_STATE_DMAREQ_1 BSP_BIT32(2)
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#define I2S_STATE_RX_LEVEL_GET(reg) BSP_FLD32GET(reg, 8, 11)
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#define I2S_STATE_TX_LEVEL_GET(reg) BSP_FLD32GET(reg, 16, 19)
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/** @} */
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/**
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* @name I2S DMA Configuration
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*
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* @{
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*/
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#define I2S_DMA_RX_ENABLE BSP_BIT32(0)
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#define I2S_DMA_TX_ENABLE BSP_BIT32(1)
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#define I2S_DMA_RX_DEPTH(val) BSP_FLD32(val, 8, 11)
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#define I2S_DMA_TX_DEPTH(val) BSP_FLD32(val, 16, 19)
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/** @} */
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/**
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* @name I2S Interrupt Request Control
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*
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* @{
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*/
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#define I2S_IRQ_RX BSP_BIT32(0)
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#define I2S_IRQ_TX BSP_BIT32(1)
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#define I2S_IRQ_RX_DEPTH(val) BSP_FLD32(val, 8, 11)
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#define I2S_IRQ_TX_DEPTH(val) BSP_FLD32(val, 16, 19)
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/** @} */
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/**
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* @name I2S Transmit and Receive Clock Rate
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*
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* @{
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*/
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#define LPC24XX_I2S_RATE(val) BSP_FLD32(val, 0, 9)
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#define LPC32XX_I2S_RATE_X_DIVIDER(val) BSP_FLD32(val, 0, 7)
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#define LPC32XX_I2S_RATE_Y_DIVIDER(val) BSP_FLD32(val, 8, 15)
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/** @} */
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/** @} */
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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#endif /* LIBBSP_ARM_SHARED_LPC_I2S_H */
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