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cb4fdffe1643980f52577ffbaf13a1560b689c72
rtems/bsps/m68k/av5282/start/start.S
Joel Sherrill cb4fdffe16 m68k/bsps/av5282: Change license to BSD-2 
Updates #3053.
2022-07-11 17:14:47 -05:00

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/* SPDX-License-Identifier: BSD-2-Clause */
/*
* uC5282 startup code
*
* This file contains the entry point for the application.
* The name of this entry point is compiler dependent.
* It jumps to the BSP which is responsible for performing
* all initialization.
*/
/*
* COPYRIGHT (c) 1989-2014.
* On-Line Applications Research Corporation (OAR).
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <bsp.h>
#include <rtems/asm.h>
#define SRAM_SIZE (64*1024)
#define DEFAULT_IPSBAR 0x40000000
BEGIN_CODE
#define INITIAL_STACK __SRAMBASE+SRAM_SIZE-4
PUBLIC (INTERRUPT_VECTOR)
SYM(INTERRUPT_VECTOR):
.long INITIAL_STACK | 0: Initial 'SSP'
.long start | 1: Initial PC
.long SYM(_uhoh) | 2: Bus error
.long SYM(_uhoh) | 3: Address error
.long SYM(_uhoh) | 4: Illegal instruction
.long SYM(_uhoh) | 5: Zero division
.long SYM(_uhoh) | 6: CHK, CHK2 instruction
.long SYM(_uhoh) | 7: TRAPcc, TRAPV instructions
.long SYM(_uhoh) | 8: Privilege violation
.long SYM(_uhoh) | 9: Trace
.long SYM(_uhoh) | 10: Line 1010 emulator
.long SYM(_uhoh) | 11: Line 1111 emulator
.long SYM(_uhoh) | 12: Hardware breakpoint
.long SYM(_uhoh) | 13: Reserved for coprocessor violation
.long SYM(_uhoh) | 14: Format error
.long SYM(_uhoh) | 15: Uninitialized interrupt
.long SYM(_uhoh) | 16: Unassigned, reserved
.long SYM(_uhoh) | 17:
.long SYM(_uhoh) | 18:
.long SYM(_uhoh) | 19:
.long SYM(_uhoh) | 20:
.long SYM(_uhoh) | 21:
.long SYM(_uhoh) | 22:
.long SYM(_uhoh) | 23:
.long SYM(_spuriousInterrupt) | 24: Spurious interrupt
.long SYM(_uhoh) | 25: Level 1 interrupt autovector
.long SYM(_uhoh) | 26: Level 2 interrupt autovector
.long SYM(_uhoh) | 27: Level 3 interrupt autovector
.long SYM(_uhoh) | 28: Level 4 interrupt autovector
.long SYM(_uhoh) | 29: Level 5 interrupt autovector
.long SYM(_uhoh) | 30: Level 6 interrupt autovector
.long SYM(_uhoh) | 31: Level 7 interrupt autovector
.long SYM(_uhoh) | 32: Trap instruction (0-15)
.long SYM(_uhoh) | 33:
.long SYM(_uhoh) | 34:
.long SYM(_uhoh) | 35:
.long SYM(_uhoh) | 36:
.long SYM(_uhoh) | 37:
.long SYM(_uhoh) | 38:
.long SYM(_uhoh) | 39:
.long SYM(_uhoh) | 40:
.long SYM(_uhoh) | 41:
.long SYM(_uhoh) | 42:
.long SYM(_uhoh) | 43:
.long SYM(_uhoh) | 44:
.long SYM(_uhoh) | 45:
.long SYM(_uhoh) | 46:
.long SYM(_uhoh) | 47:
.long SYM(_uhoh) | 48: Reserved for coprocessor
.long SYM(_uhoh) | 49:
.long SYM(_uhoh) | 50:
.long SYM(_uhoh) | 51:
.long SYM(_uhoh) | 52:
.long SYM(_uhoh) | 53:
.long SYM(_uhoh) | 54:
.long SYM(_uhoh) | 55:
.long SYM(_uhoh) | 56:
.long SYM(_uhoh) | 57:
.long SYM(_uhoh) | 58:
.long SYM(_uhoh) | 59: Unassigned, reserved
.long SYM(_uhoh) | 60:
.long SYM(_uhoh) | 61:
.long SYM(_uhoh) | 62:
.long SYM(_uhoh) | 63:
.long SYM(_spuriousInterrupt) | 64: User spurious handler
.long SYM(_uhoh) | 65:
.long SYM(_uhoh) | 66:
.long SYM(_uhoh) | 67:
.long SYM(_uhoh) | 68:
.long SYM(_uhoh) | 69:
.long SYM(_uhoh) | 70:
.long SYM(_uhoh) | 71:
.long SYM(_uhoh) | 72:
.long SYM(_uhoh) | 73:
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.long SYM(_uhoh) | 76:
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.long SYM(_uhoh) | 83:
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.long SYM(_uhoh) | 255:
/*
* Default trap handler
* With an oscilloscope you can see AS* stop
*/
.align 4
PUBLIC (_uhoh)
SYM(_uhoh):
nop | Leave spot for breakpoint
stop #0x2700 | Stop with interrupts disabled
bra.w SYM(_uhoh) | Stuck forever
.align 4
PUBLIC (_spuriousInterrupt)
SYM(_spuriousInterrupt):
addql #1,SYM(_M68kSpuriousInterruptCount)
rte
/***************************************************************************
Function : start
Description : setup the internal SRAM for use and setup the INITIAL STACK ptr.
Also enable the internal peripherals
***************************************************************************/
.align 4
PUBLIC (start)
SYM(start):
move.w #0x0000,d0 | Turn off watchdog timer
move.w d0, (0x40140000)
move.w #0x2000,d0 | Set system frequency to 58960000
move.w d0, (0x40120000)
move.w #0x2700,sr | Disable interrupts
move.l #__SRAMBASE+1,d0 | Enable the MCF5282 internal SRAM
movec d0,%rambar | ...so we have a stack
move.l #(INITIAL_STACK),sp | Overwrite the fake stack pointer
/*
* If we're being started by the debugger, and the debugger has
* moved the IPSBAR, we're doomed........
*/
move.l #__IPSBAR+1,d0 | Enable the MCF5282 internal peripherals
move.l d0,DEFAULT_IPSBAR
/*
* Remainder of the startup code is handled by C code
*/
jmp SYM(Init5282) | Start C code (which never returns)
/***************************************************************************
Function : CopyDataClearBSSAndStart
Description : Copy DATA segment, Copy SRAM segment, clear BSS segment,
start C program. Assume that DATA and BSS sizes are multiples of 4.
***************************************************************************/
.align 4
PUBLIC (CopyDataClearBSSAndStart)
SYM(CopyDataClearBSSAndStart):
lea SYM(_data_dest_start),a0 | Get start of DATA in RAM
lea SYM(_data_src_start),a2 | Get start of DATA in ROM
cmpl a0,a2 | Are they the same?
beq.s NODATACOPY | Yes, no copy necessary
lea SYM(_data_dest_end),a1 | Get end of DATA in RAM
bra.s DATACOPYLOOPTEST | Branch into copy loop
DATACOPYLOOP:
movel a2@+,a0@+ | Copy word from ROM to RAM
DATACOPYLOOPTEST:
cmpl a1,a0 | Done?
bcs.s DATACOPYLOOP | No, skip
NODATACOPY:
/* Now, clear BSS */
lea _clear_start,a0 | Get start of BSS
lea _clear_end,a1 | Get end of BSS
clrl d0 | Value to set
bra.s ZEROLOOPTEST | Branch into clear loop
ZEROLOOP:
movel d0,a0@+ | Clear a word
ZEROLOOPTEST:
cmpl a1,a0 | Done?
bcs.s ZEROLOOP | No, skip
/*
* Right : Now we're ready to boot RTEMS
*/
move.l #_ISR_Stack_area_end,sp | Use configuration defined stack
clrl d0 | Pass in null to all boot_card() params
movel d0,a7@- | command line
jsr SYM(boot_card) | Call C boot_card function to startup RTEMS
movel a7@+,d0
MULTI_TASK_EXIT:
nop
nop
trap #14
bra MULTI_TASK_EXIT
END_CODE
.align 2
BEGIN_DATA_DCL
.align 2
PUBLIC (_M68kSpuriousInterruptCount)
SYM (_M68kSpuriousInterruptCount):
.long 0
END_DATA_DCL
END
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