forked from Imagelibrary/rtems
143 lines
5.5 KiB
C
143 lines
5.5 KiB
C
/*
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* Header file for RTEMS SATCAN FPGA driver
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*
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* COPYRIGHT (c) 2009.
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* Cobham Gaisler AB.
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#ifndef __SATCAN_H__
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#define __SATCAN_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Config structure passed to SatCAN_init(..) */
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typedef struct {
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/* Configuration */
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int nodeno;
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int dps;
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/* Callback functions */
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void (*ahb_irq_callback)(void);
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void (*pps_irq_callback)(void);
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void (*m5_irq_callback)(void);
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void (*m4_irq_callback)(void);
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void (*m3_irq_callback)(void);
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void (*m2_irq_callback)(void);
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void (*m1_irq_callback)(void);
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void (*sync_irq_callback)(void);
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void (*can_irq_callback)(unsigned int fifo);
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} satcan_config;
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#define SATCAN_HEADER_SIZE 4
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#define SATCAN_HEADER_NMM_POS 3
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#define SATCAN_PAYLOAD_SIZE 8
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/* SatCAN message */
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typedef struct {
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unsigned char header[SATCAN_HEADER_SIZE]; /* Header of SatCAN message */
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unsigned char payload[SATCAN_PAYLOAD_SIZE]; /* Payload of SatCAN message */
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} satcan_msg;
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/* SatCAN modify register structure */
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typedef struct {
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unsigned int reg;
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unsigned int val;
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} satcan_regmod;
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/* Driver interface */
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int satcan_register(satcan_config *conf);
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/* SatCAN interrupt IDs */
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#define SATCAN_IRQ_NONACT_TO_ACT 0
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#define SATCAN_IRQ_ACTIVE_TO_NONACT 1
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#define SATCAN_IRQ_STR1_TO_DPS 2
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#define SATCAN_IRQ_DPS_TO_STR1 3
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#define SATCAN_IRQ_STR2_TO_DPS 4
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#define SATCAN_IRQ_DPS_TO_STR2 5
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#define SATCAN_IRQ_STR3_TO_DPS 6
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#define SATCAN_IRQ_DPS_TO_STR3 7
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#define SATCAN_IRQ_PLD1_TO_DPS 8
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#define SATCAN_IRQ_DPS_TO_PLD1 9
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#define SATCAN_IRQ_PLD2_TO_DPS 10
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#define SATCAN_IRQ_DPS_TO_PLD2 11
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#define SATCAN_IRQ_SYNC 16
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#define SATCAN_IRQ_TIME_MARKER1 17
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#define SATCAN_IRQ_TIME_MARKER2 18
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#define SATCAN_IRQ_TIME_MARKER3 19
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#define SATCAN_IRQ_TIME_MARKER4 20
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#define SATCAN_IRQ_TIME_MARKER5 21
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#define SATCAN_IRQ_EOD1 22
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#define SATCAN_IRQ_EOD2 23
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#define SATCAN_IRQ_TOD 24
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#define SATCAN_IRQ_CRITICAL 25
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/* IOC */
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#define SATCAN_IOC_DMA_2K 1 /* Use DMA area for 2K messages */
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#define SATCAN_IOC_DMA_8K 2 /* Use DMA area for 8K messages */
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#define SATCAN_IOC_GET_REG 3 /* Provides direct read access to all core registers */
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#define SATCAN_IOC_SET_REG 4 /* Provides direct write access to all core registers */
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#define SATCAN_IOC_OR_REG 5 /* Provides direct read access to all core registers */
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#define SATCAN_IOC_AND_REG 6 /* Provides direct write access to all core registers */
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#define SATCAN_IOC_EN_TX1_DIS_TX2 7 /* Enable DMA TX channel 1, Disable DMA TX channel 2 */
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#define SATCAN_IOC_EN_TX2_DIS_TX1 8 /* Enable DMA TX channel 2, Disable DMA TX channel 1 */
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#define SATCAN_IOC_GET_DMA_MODE 9 /* Returns the current DMA mode */
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#define SATCAN_IOC_SET_DMA_MODE 10 /* Sets the DMA mode */
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#define SATCAN_IOC_ACTIVATE_DMA 11 /* Directly activate DMA channel */
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#define SATCAN_IOC_DEACTIVATE_DMA 12 /* Directly deactivate DMA channel */
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#define SATCAN_IOC_DMA_STATUS 13 /* Returns status of directly activated DMA */
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#define SATCAN_IOC_GET_DOFFSET 14 /* Get TX DMA offset */
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#define SATCAN_IOC_SET_DOFFSET 15 /* Set TX DMA offset */
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#define SATCAN_IOC_GET_TIMEOUT 16 /* Set TX DMA timeout */
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#define SATCAN_IOC_SET_TIMEOUT 17 /* Get TX DMA timeout */
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/* Values used to select core register with IOC_SET_REG/IOC_GET_REG */
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#define SATCAN_SWRES 0 /* Software reset */
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#define SATCAN_INT_EN 1 /* Interrupt enable */
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#define SATCAN_FIFO 3 /* FIFO read */
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#define SATCAN_FIFO_RES 4 /* FIFO reset */
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#define SATCAN_TSTAMP 5 /* Current time stamp */
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#define SATCAN_CMD0 6 /* Command register 0 */
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#define SATCAN_CMD1 7 /* Command register 1 */
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#define SATCAN_START_CTC 8 /* Start cycle time counter */
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#define SATCAN_RAM_BASE 9 /* RAM offset address */
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#define SATCAN_STOP_CTC 10 /* Stop cycle time counter / DPS active status */
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#define SATCAN_DPS_ACT 10 /* Stop cycle time counter / DPS active status */
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#define SATCAN_PLL_RST 11 /* DPLL reset */
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#define SATCAN_PLL_CMD 12 /* DPLL command */
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#define SATCAN_PLL_STAT 13 /* DPLL status */
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#define SATCAN_PLL_OFF 14 /* DPLL offset */
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#define SATCAN_DMA 15 /* DMA channel enable */
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#define SATCAN_DMA_TX_1_CUR 16 /* DMA channel 1 TX current address */
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#define SATCAN_DMA_TX_1_END 17 /* DMA channel 1 TX end address */
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#define SATCAN_DMA_TX_2_CUR 18 /* DMA channel 2 TX current address */
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#define SATCAN_DMA_TX_2_END 19 /* DMA channel 2 TX end address */
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#define SATCAN_RX 20 /* CAN RX enable / Filter start ID */
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#define SATCAN_FILTER_START 20 /* CAN RX enable / Filter start ID */
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#define SATCAN_FILTER_SETUP 21 /* Filter setup / Filter stop ID */
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#define SATCAN_FILTER_STOP 21 /* Filter setup / Filter stop ID */
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#define SATCAN_WCTRL 32 /* Wrapper status/control register */
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#define SATCAN_WIPEND 33 /* Wrapper interrupt pending register */
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#define SATCAN_WIMASK 34 /* Wrapper interrupt mask register */
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#define SATCAN_WAHBADDR 35 /* Wrapper AHB address register */
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/* Values used to communicate DMA mode */
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#define SATCAN_DMA_MODE_USER 0
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#define SATCAN_DMA_MODE_SYSTEM 1
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/* Values used to directly activate DMA channel */
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#define SATCAN_DMA_ENABLE_TX1 1
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#define SATCAN_DMA_ENABLE_TX2 2
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#ifdef __cplusplus
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}
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#endif
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#endif /* __SATCAN_H__ */
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