forked from Imagelibrary/rtems
918 lines
26 KiB
ArmAsm
918 lines
26 KiB
ArmAsm
/*===============================================================*\
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| Project: RTEMS generic MPC5200 BSP |
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+-----------------------------------------------------------------+
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| File: $File$
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+-----------------------------------------------------------------+
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| Partially based on the code references which are named below. |
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| Adaptions, modifications, enhancements and any recent parts of |
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| the code are: |
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| Copyright (c) 2005 |
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| Embedded Brains GmbH |
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| Obere Lagerstr. 30 |
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| D-82178 Puchheim |
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| Germany |
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| rtems@embedded-brains.de |
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+-----------------------------------------------------------------+
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| The license and distribution terms for this file may be |
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| found in the file LICENSE in this distribution or at |
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| |
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| http://www.rtems.com/license/LICENSE. |
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| |
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+-----------------------------------------------------------------+
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| this file contains the startup assembly code |
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+-----------------------------------------------------------------+
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| date history ID |
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| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
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| 01.12.05 creation doe |
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|*****************************************************************|
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|*CVS information: |
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|*(the following information is created automatically, |
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|*do not edit here) |
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|*****************************************************************|
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|* $Log$
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|* Revision 1.10 2005/12/09 08:57:03 thomas
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|* added/modifed file headers
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|*
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|* Revision 1.9 2005/12/06 14:11:12 thomas
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|* added EB file headers
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|*
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*
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|*****************************************************************|
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\*===============================================================*/
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/***********************************************************************/
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/* */
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/* Module: start.S */
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/* Date: 07/17/2003 */
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/* Purpose: RTEMS MPC5x00 CPU assembly startup */
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/* */
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/*---------------------------------------------------------------------*/
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/* */
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/* Description: This file contains the assembler portion of MPC5x00 */
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/* startup code */
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/* */
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/*---------------------------------------------------------------------*/
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/* */
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/* Code */
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/* References: startup code for Motorola PQII ADS board */
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/* Module: start.S */
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/* Project: RTEMS 4.6.0pre1 / MCF8260ads BSP */
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/* Version 1.2 */
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/* Date: 04/18/2002 */
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/* */
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/* Author(s) / Copyright(s): */
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/* */
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/* Modified for the Motorola PQII ADS board by */
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/* Andy Dachs <a.dachs@sstl.co.uk> 23-11-00. */
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/* Surrey Satellite Technology Limited */
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/* */
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/* I have a proprietary bootloader programmed into the flash */
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/* on the board which initialises the SDRAM prior to calling */
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/* this function. */
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/* */
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/* This file is based on the one by Jay Monkman (jmonkman@fracsa.com)*/
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/* which in turn was based on the dlentry.s file for the Papyrus BSP,*/
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/* written by: */
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/* */
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/* Author: Andrew Bray <andy@i-cubed.co.uk> */
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/* */
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/* COPYRIGHT (c) 1995 by i-cubed ltd. */
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/* */
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/* To anyone who acknowledges that this file is provided "AS IS" */
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/* without any express or implied warranty: */
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/* permission to use, copy, modify, and distribute this file */
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/* for any purpose is hereby granted without fee, provided that */
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/* the above copyright notice and this notice appears in all */
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/* copies, and that the name of i-cubed limited not be used in */
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/* advertising or publicity pertaining to distribution of the */
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/* software without specific, written prior permission. */
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/* i-cubed limited makes no representations about the suitability */
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/* of this software for any purpose. */
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/* */
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/*---------------------------------------------------------------------*/
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/* */
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/* Partially based on the code references which are named above. */
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/* Adaptions, modifications, enhancements and any recent parts of */
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/* the code are under the right of */
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/* */
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/* IPR Engineering, Dachauer Stra<72>e 38, D-80335 M<>nchen */
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/* Copyright(C) 2003 */
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/* */
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/*---------------------------------------------------------------------*/
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/* */
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/* IPR Engineering makes no representation or warranties with */
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/* respect to the performance of this computer program, and */
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/* specifically disclaims any responsibility for any damages, */
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/* special or consequential, connected with the use of this program. */
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/* */
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/*---------------------------------------------------------------------*/
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/* */
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/* Version history: 1.0 */
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/* */
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/***********************************************************************/
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#include <rtems/asm.h>
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#include <rtems/powerpc/cache.h>
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#include <rtems/powerpc/registers.h>
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#include "../include/mpc5200.h"
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#include "../include/bsp.h"
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/* Macro definitions to load a register with a 32-bit address.
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Both functions identically. Sometimes one mnemonic is more
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appropriate than the other.
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reg -> register to load
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value -> value to be loaded
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LA reg,value ("Load Address")
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LWI reg,value ("Load Word Immediate") */
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.macro LA reg, value
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lis \reg , \value@h
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ori \reg , \reg, \value@l
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sync
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.endm
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.macro LWI reg, value
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lis \reg , \value@h
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ori \reg , \reg, \value@l
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sync
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.endm
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/* Macro definitions to test, set or clear a single
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bit or bit pattern in a given 32bit GPR.
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reg1 -> register content to be tested
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reg2 -> 2nd register only needed for computation
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mask -> any bit pattern */
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.macro TSTBITS reg1, reg2, mask /* Match is indicated by EQ=0 (CR) */
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LWI \reg2, \mask /* Unmatch is indicated by EQ=1 (CR) */
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and \reg1, \reg1, \reg2
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cmplw \reg1, \reg2
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sync
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.endm
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.macro SETBITS reg1, reg2, mask
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LWI \reg2, \mask
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or \reg1, \reg1, \reg2
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sync
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.endm
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.macro CLRBITS reg1, reg2, mask
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LWI \reg2, \mask
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andc \reg1, \reg1, \reg2
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sync
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.endm
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/* Some register offsets of MPC5x00 memory map registers */
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.set CS0STR, 0x04
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.set CS0STP, 0x08
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.set CS1STR, 0x0C
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.set CS1STP, 0x10
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.set SDRAMCS0, 0x34
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.set SDRAMCS1, 0x38
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.set BOOTSTR, 0x4C
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.set BOOTSTP, 0x50
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.set ADREN, 0x54
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.set CSSR0, 0x58 /* Critical Interrupt SSR0 (603le only) */
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.set CSSR1, 0x59 /* Critical Interrupt SSR1 (603le only) */
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.set CFG, 0x20C
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.set CSBOOTROM, 0x300
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.set CSCONTROL, 0x318
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.set CS1CONF, 0x304
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/* Register offsets of MPC5x00 SDRAM memory controller registers */
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.set MOD, 0x100
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.set CTRL, 0x104
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.set CFG1, 0x108
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.set CFG2, 0x10C
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.set ADRSEL, 0x110
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/* Register offsets of MPC5x00 GPIO registers needed */
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.set GPIOPCR, 0xb00
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.set GPIOWE, 0xc00
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.set GPIOWOD, 0xc04
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.set GPIOWDD, 0xc08
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.set GPIOWDO, 0xc0c
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.set GPIOSEN, 0xb04
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.set GPIOSDD, 0xb0c
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.set GPIOSDO, 0xb10
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/* Register offsets of MPC5x00 Arbiter registers */
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.set ARBCFG, 0x1f40
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.set ARBMPREN, 0x1f64
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.set ARBMPRIO, 0x1f68
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.set ARBSNOOP, 0x1f70
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/* Some bit encodings for MGT5100 registers */
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.set ADREN_SDRAM_EN, (1<<22)
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.set ADREN_BOOT_EN, (1<<25)
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.set ADREN_CS0_EN, (1<<16)
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.set ADREN_CS1_EN, (1<<17)
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.set CTRL_PRECHARGE, (1<<1)
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.set CTRL_REFRESH, (1<<2)
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.set CTRL_BA1, (1<<31)
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.set CSCONF_CE, (1<<12)
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/* Some fixed values for MPC5x00 registers */
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.set CSBOOTROM_VAL, 0x0101D910
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.set CSCONTROL_VAL, 0x91000000
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.set CFG_VAL, 0x00000100
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.extern _bss_start
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.extern _bss_size
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.extern _data_start
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.extern _data_size
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.extern _text_start
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.extern _text_size
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/*.extern _s_got*/
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.extern boot_card
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.extern MBAR
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.section ".entry"
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PUBLIC_VAR (start)
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start:
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/* 1st: initialization work (common for RAM/ROM startup) */
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mfmsr r30
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SETBITS r30, r29, MSR_ME|MSR_RI
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CLRBITS r30, r29, MSR_EE
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mtmsr r30 /* Set RI/ME, Clr EE in MSR */
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#if defined(HAS_UBOOT)
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/* store pointer to UBoot bd_info board info structure */
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LWI r31,uboot_bdinfo_ptr
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stw r3,0(r31)
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#endif /* defined(HAS_UBOOT) */
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#if defined(NEED_LOW_LEVEL_INIT)
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/* initialize the MBAR (common RAM/ROM startup) */
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LWI r31, MBAR_RESET
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LWI r29, MBAR
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rlwinm r30, r29,16,16,31
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stw r30, 0(r31) /* Set the MBAR */
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#endif
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LWI r31, MBAR /* set r31 to current MBAR */
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/* init GPIOPCR */
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lwz r29,GPIOPCR(r31)
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LWI r30, GPIOPCR_INITMASK
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not r30,r30
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and r29,r29,r30
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LWI r30, GPIOPCR_INITVAL
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or r29,r29,r30
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stw r29, GPIOPCR(r31)
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/* further initialization work (common RAM/ROM startup) */
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bl TLB_init /* Initialize TLBs */
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bl FID_DCache /* Flush, inhibit and disable data cache */
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bl IDUL_ICache /* Inhibit, disable and unlock instruction cache */
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bl FPU_init /* Initialize FPU */
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#if defined(NEED_LOW_LEVEL_INIT)
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bl SPRG_init /* Initialize special purpose registers */
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#endif
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#if defined(NEED_LOW_LEVEL_INIT)
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/* detect RAM/ROM startup (common for RAM/ROM startup) */
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LWI r20, ROM_START /* set the relocation offset */
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LWI r30, CFG_VAL /* get CFG register content */
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lwz r30, CFG(r31) /* set SDRAM single data rate / XLB_CLK=FVCO/4 / IPB_CLK=XLB_CLK/2 / PCICLK=IPB_CLK */
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lwz r30, ADREN(r31) /* get content of ADREN */
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TSTBITS r30, r29, ADREN_BOOT_EN
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bne skip_ROM_start /* If BOOT_ROM is not enabled, skip further initialization */
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/* do some board dependent configuration (unique for ROM startup) */
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bl SPRG_brk_init /* Initialize special purpose onchip breakpoint registers */
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LWI r30, CSCONTROL_VAL /* get CSCONTROL register content */
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stw r30, CSCONTROL(r31) /* enable internal/external bus error and master for CS */
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#ifdef RSM5LOG
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LWI r30, CSBOOTROM_VAL
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stw r30, CSBOOTROM(r31) /* Set CSBOOTROM */
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#endif
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/* FIXME: map BOOT ROM into final location with CS0 registers */
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LWI r30, ROM_START
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rlwinm r30, r30,17,15,31
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stw r30, CS0STR(r31) /* Set CS0STR */
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LWI r30, ROM_END
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rlwinm r30, r30,17,15,31
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stw r30, CS0STP(r31) /* Set CS0STP */
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lwz r30, ADREN(r31) /* get content of ADREN */
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SETBITS r30, r29, ADREN_CS0_EN
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stw r30, ADREN(r31) /* enable CS0 mapping */
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isync
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/* jump to same code in final BOOT ROM location */
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LWI r30, reloc_in_CS0
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LWI r29, RAM_START
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sub r30,r30,r29
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LWI r29, ROM_START
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add r30,r30,r29
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mtctr r30
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bctr
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reloc_in_CS0:
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/* disable CSBOOT (or map it to CS0 range) */
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lwz r30, ADREN(r31) /* get content of ADREN */
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CLRBITS r30, r29, ADREN_BOOT_EN
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stw r30, ADREN(r31) /* disable BOOT mapping */
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/* init SDRAM */
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LWI r30, RAM_START
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ori r30,r30,0x1a /* size code: bank is 128MByte */
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stw r30,SDRAMCS0(r31) /* Set SDRAMCS0 */
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LWI r30,(RAM_END+1-RAM_START)/2
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ori r30,r30,0x1a /* size code: bank is 128MByte */
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stw r30, SDRAMCS1(r31) /* Set SDRAMCS1 */
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bl SDRAM_init /* Initialize SDRAM controller */
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/* init arbiter and stuff... */
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LWI r30, 0x8000a06e
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stw r30, ARBCFG(r31) /* Set ARBCFG */
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LWI r30, 0x000000ff
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stw r30, ARBMPREN(r31) /* Set ARBMPREN */
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LWI r30, 0x00001234
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stw r30, ARBMPRIO(r31) /* Set ARBPRIO */
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LWI r30, 0x0000001e
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stw r30, ARBSNOOP(r31) /* Set ARBSNOOP */
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/* copy .text section from ROM to RAM location (unique for ROM startup) */
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LA r30, _text_start /* get start address of text section in RAM */
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add r30, r20, r30 /* get start address of text section in ROM (add reloc offset) */
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LA r29, _text_start /* get start address of text section in RAM */
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LA r28, _text_size /* get size of RAM image */
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bl copy_image /* copy text section from ROM to RAM location */
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/* copy .data section from ROM to RAM location (unique for ROM startup) */
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LA r30, _data_start /* get start address of data section in RAM */
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add r30, r20, r30 /* get start address of data section in ROM (add reloc offset) */
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LA r29, _data_start /* get start address of data section in RAM */
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LA r28, _data_size /* get size of RAM image */
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bl copy_image /* copy initialized data section from ROM to RAM location */
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LA r29, remap_rom /* get compile time address of label */
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mtlr r29
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blrl /* now further execution RAM */
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remap_rom:
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/* remap BOOT ROM to CS0 (common for RAM/ROM startup) */
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lwz r30, CSBOOTROM(r31) /* get content of CSBOOTROM */
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CLRBITS r30, r29, CSCONF_CE
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stw r30, CSBOOTROM(r31) /* disable BOOT CS */
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||
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lwz r30, ADREN(r31) /* get content of ADREN */
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mr r29, r30 /* move content of r30 to r29 */
|
||
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||
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LWI r30, ADREN_BOOT_EN /* mask ADREN_BOOT_EN */
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||
andc r29,r29,r30
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||
|
||
|
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LWI r30, ADREN_CS0_EN /* unmask ADREN_CS0_EN */
|
||
or r29,r29,r30
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||
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||
|
||
stw r29,ADREN(r31) /* Simultaneous enable CS0 and disable BOOT address space */
|
||
|
||
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||
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lwz r30, CSBOOTROM(r31) /* get content of CSBOOTROM */
|
||
|
||
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SETBITS r30, r29, CSCONF_CE
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||
stw r30, CSBOOTROM(r31) /* disable BOOT CS */
|
||
|
||
|
||
|
||
skip_ROM_start:
|
||
/* configure external DPRAM CS1 */
|
||
LWI r30,0xFFFFFB10
|
||
stw r30,CS1CONF(r31)
|
||
|
||
/* map external DPRAM (CS1) */
|
||
LWI r30,(DPRAM_START>>16)
|
||
stw r30,CS1STR(r31)
|
||
|
||
LWI r30,((DPRAM_END)>>16)
|
||
stw r30,CS1STP(r31)
|
||
|
||
lwz r30, ADREN(r31) /* get content of ADREN */
|
||
|
||
LWI r29, ADREN_CS1_EN /* unmask ADREN_CS1_EN */
|
||
or r30,r30,r29
|
||
|
||
stw r30,ADREN(r31) /* enable CS1 */
|
||
|
||
/* clear entire on chip SRAM (unique for ROM startup) */
|
||
LWI r30, (MBAR+ONCHIP_SRAM_OFFSET) /* get start address of onchip SRAM */
|
||
LWI r29, ONCHIP_SRAM_SIZE /* get size of onchip SRAM */
|
||
|
||
bl clr_mem /* Clear onchip SRAM */
|
||
|
||
#endif /* defined(RSM5LOG) */
|
||
/* clear .bss section (unique for ROM startup) */
|
||
LWI r30, _bss_start /* get start address of bss section */
|
||
LWI r29, _bss_size /* get size of bss section */
|
||
|
||
|
||
bl clr_mem /* Clear the bss section */
|
||
|
||
|
||
/* set stack pointer (common for RAM/ROM startup) */
|
||
LA r1, _text_start
|
||
addi r1, r1, -0x10 /* Set up stack pointer = beginning of text section - 0x10 */
|
||
|
||
|
||
/* enable dynamic power management(common for RAM/ROM startup) */
|
||
bl PPC_HID0_rd /* Get the content of HID0 */
|
||
|
||
SETBITS r30, r29, HID0_DPM
|
||
bl PPC_HID0_wr /* Set DPM in HID0 */
|
||
|
||
/* clear arguments and do further init. in C (common for RAM/ROM startup) */
|
||
xor r3, r3, r3
|
||
xor r4, r4, r4 /* Clear argc and argv */
|
||
|
||
#if 1
|
||
bl SYM (boot_card) /* Call the first C routine */
|
||
#endif
|
||
|
||
#if defined(BRS5L)
|
||
twiddle:
|
||
b twiddle /* We don't expect to return from boot_card but if we do */
|
||
/* wait here for watchdog to kick us into hard reset */
|
||
|
||
SDRAM_init:
|
||
#if defined (BRS5L)
|
||
/* set GPIO_WKUP7 pin low for 66MHz buffering */
|
||
/* or high for 133MHz registered buffering */
|
||
LWI r30, 0x80000000
|
||
|
||
lwz r29, GPIOWE(r31)
|
||
or r29,r29,r30 /* set bit 0 in r29/GPIOWE */
|
||
stw r29,GPIOWE(r31)
|
||
|
||
lwz r29, GPIOWOD(r31)
|
||
andc r29,r29,r30 /* clear bit 0 in r29/GPIOWOD */
|
||
stw r29,GPIOWOD(r31)
|
||
|
||
lwz r29, GPIOWDO(r31)
|
||
andc r29,r29,r30 /* clear bit 0 in r29/GPIOWDO */
|
||
stw r29,GPIOWDO(r31)
|
||
|
||
lwz r29, GPIOWDD(r31)
|
||
or r29,r29,r30 /* set bit 0 in r29/GPIOWDD */
|
||
stw r29,GPIOWDD(r31)
|
||
|
||
/* activate MEM_CS1 output */
|
||
lwz r29, GPIOPCR(r31)
|
||
or r29,r29,r30 /* set bit 0 in r29/GPIOPCR */
|
||
stw r29,GPIOPCR(r31)
|
||
|
||
#endif
|
||
#if 0
|
||
LWI r30, 0xC2222600 /* Single Read2Read/Write delay=0xC, Single Write2Read/Prec. delay=0x2 */
|
||
stw r30, CFG1(r31) /* Read CAS latency=0x2, Active2Read delay=0x2, Prec.2active delay=0x2 */
|
||
/* Refr.2No-Read delay=0x06, Write latency=0x0 */
|
||
#else
|
||
/* See Erratum 342/339 in MPC5200_Errata_L25R_3_June.pdf: */
|
||
/* set 5 delays to their maximum to support two banks */
|
||
LWI r30, 0xCC222600 /* Single Read2Read/Write delay=0xC, Single Write2Read/Prec. delay=0x2 */
|
||
stw r30, CFG1(r31) /* Read CAS latency=0x2, Active2Read delay=0x2, Prec.2active delay=0x2 */
|
||
/* Refr.2No-Read delay=0x06, Write latency=0x0 */
|
||
#endif
|
||
|
||
LWI r30, 0xCCC70004 /* Burst2Read Prec.delay=0x8, Burst Write delay=0x8 */
|
||
stw r30, CFG2(r31) /* Burst Read2Write delay=0xB, Burst length=0x7, Read Tap=0x4 */
|
||
|
||
#ifdef RSM5LOG
|
||
LWI r30, 0xD1470000 /* Mode Set enabled, Clock enabled, Auto refresh enabled, Mem. data drv */
|
||
stw r30, CTRL(r31) /* Refresh counter=0xFFFF */
|
||
|
||
|
||
#else
|
||
LWI r30, 0xD04F0000 /* Mode Set enabled, Clock enabled, Auto refresh enabled, Mem. data drv */
|
||
stw r30, CTRL(r31) /* Refresh counter=0xFFFF */
|
||
|
||
|
||
#endif
|
||
lwz r30, CTRL(r31)
|
||
|
||
|
||
SETBITS r30, r29, CTRL_PRECHARGE /* send two times precharge */
|
||
stw r30, CTRL(r31)
|
||
|
||
|
||
stw r30, CTRL(r31)
|
||
|
||
|
||
|
||
lwz r30, CTRL(r31)
|
||
|
||
|
||
SETBITS r30, r29, CTRL_REFRESH /* send two times refresh */
|
||
stw r30, CTRL(r31)
|
||
|
||
|
||
stw r30, CTRL(r31)
|
||
|
||
|
||
|
||
LWI r30, 0x008D0000 /* Op.Mode=0x0, Read CAS latency=0x2, Burst length=0x3, Write strobe puls */
|
||
stw r30, MOD(r31)
|
||
|
||
|
||
|
||
lwz r30, CTRL(r31) /* Clock enabled, Auto refresh enabled, Mem. data drv. Refresh counter=0xFFFF */
|
||
|
||
|
||
CLRBITS r30, r29, CTRL_BA1
|
||
stw r30, CTRL(r31)
|
||
|
||
|
||
|
||
blr
|
||
|
||
|
||
copy_image:
|
||
mr r27, r28
|
||
srwi r28, r28, 2
|
||
mtctr r28
|
||
|
||
|
||
slwi r28, r28, 2
|
||
sub r27, r27, r28 /* maybe some residual bytes */
|
||
|
||
|
||
copy_image_word:
|
||
lswi r28, r30, 0x04
|
||
|
||
stswi r28, r29, 0x04 /* do word copy ROM -> RAM */
|
||
|
||
|
||
addi r30, r30, 0x04 /* increment source pointer */
|
||
addi r29, r29, 0x04 /* increment destination pointer */
|
||
|
||
bdnz copy_image_word /* decrement ctr and branch if not 0 */
|
||
|
||
cmpwi r27, 0x00 /* copy image finished ? */
|
||
beq copy_image_end;
|
||
mtctr r27 /* reload counter for residual bytes */
|
||
copy_image_byte:
|
||
lswi r28, r30, 0x01
|
||
|
||
stswi r28, r29, 0x01 /* do byte copy ROM -> RAM */
|
||
|
||
|
||
addi r30, r30, 0x01 /* increment source pointer */
|
||
addi r29, r29, 0x01 /* increment destination pointer */
|
||
|
||
bdnz copy_image_byte /* decrement ctr and branch if not 0 */
|
||
|
||
copy_image_end:
|
||
blr
|
||
#endif /* defined(RSM5LOG) */
|
||
|
||
FID_DCache:
|
||
mflr r26
|
||
|
||
bl PPC_HID0_rd
|
||
TSTBITS r30, r29, HID0_DCE
|
||
bne FID_DCache_exit /* If data cache is switched of, skip further actions */
|
||
|
||
li r29, PPC_D_CACHE /* 16 Kb data cache on 603e */
|
||
LWI r28, _text_start /* Load base address (begin of RAM) */
|
||
|
||
FID_DCache_loop_1:
|
||
lwz r27, 0(r28) /* Load data at address */
|
||
|
||
addi r28, r28, PPC_CACHE_ALIGNMENT /* increment cache line address */
|
||
subi r29, r29, PPC_CACHE_ALIGNMENT /* increment loop counter */
|
||
cmpwi r29, 0x0
|
||
bne FID_DCache_loop_1 /* Loop until cache size is reached */
|
||
|
||
li r29, PPC_D_CACHE /* 16 Kb data cache on 603e */
|
||
LWI r28, _text_start /* Reload base address (begin of RAM) */
|
||
xor r27, r27, r27
|
||
FID_DCache_loop_2:
|
||
|
||
dcbf r27, r28 /* Flush and invalidate cache */
|
||
|
||
addi r28, r28, PPC_CACHE_ALIGNMENT /* increment cache line address */
|
||
subi r29, r29, PPC_CACHE_ALIGNMENT /* increment loop counter */
|
||
cmpwi r29, 0x0
|
||
bne FID_DCache_loop_2 /* Loop around until cache size is reached */
|
||
|
||
bl PPC_HID0_rd /* Read HID0 */
|
||
CLRBITS r30, r29, HID0_DCE
|
||
bl PPC_HID0_wr /* Clear DCE */
|
||
|
||
FID_DCache_exit:
|
||
mtlr r26
|
||
blr
|
||
|
||
IDUL_ICache:
|
||
mflr r26
|
||
|
||
bl PPC_HID0_rd
|
||
TSTBITS r30, r29, HID0_ICE
|
||
bne IDUL_ICache_exit /* If instruction cache is switched of, skip further actions */
|
||
|
||
CLRBITS r30, r29, HID0_ICE
|
||
bl PPC_HID0_wr /* Disable ICE bit */
|
||
|
||
SETBITS r30, r29, HID0_ICFI
|
||
bl PPC_HID0_wr /* Invalidate instruction cache */
|
||
|
||
CLRBITS r30, r29, HID0_ICFI
|
||
bl PPC_HID0_wr /* Disable cache invalidate */
|
||
|
||
CLRBITS r30, r29, HID0_ILOCK
|
||
bl PPC_HID0_wr /* Disable instruction cache lock */
|
||
|
||
IDUL_ICache_exit:
|
||
mtlr r26
|
||
blr
|
||
|
||
|
||
TLB_init: /* Initialize translation lookaside buffers (TLBs) */
|
||
xor r30, r30, r30
|
||
xor r29, r29, r29
|
||
|
||
TLB_init_loop:
|
||
tlbie r29
|
||
tlbsync
|
||
addi r29, r29, 0x1000
|
||
addi r30, r30, 0x01
|
||
cmpli 0, 0, r30, 0x0080
|
||
bne TLB_init_loop
|
||
blr
|
||
|
||
FPU_init:
|
||
mfmsr r30 /* get content of MSR */
|
||
|
||
|
||
SETBITS r30, r29, MSR_FP
|
||
mtmsr r30 /* enable FPU and FPU exceptions */
|
||
|
||
#if 0
|
||
LA r29, RAM_START
|
||
stw r29, 0x0(r29)
|
||
#endif
|
||
|
||
lfd f0, 0(r29)
|
||
fmr f1, f0
|
||
fmr f2, f0
|
||
fmr f3, f0
|
||
fmr f4, f0
|
||
fmr f5, f0
|
||
fmr f6, f0
|
||
fmr f7, f0
|
||
fmr f8, f0
|
||
fmr f9, f0
|
||
fmr f10, f0
|
||
fmr f11, f0
|
||
fmr f12, f0
|
||
fmr f13, f0
|
||
fmr f14, f0
|
||
fmr f15, f0
|
||
fmr f16, f0
|
||
fmr f17, f0
|
||
fmr f18, f0
|
||
fmr f19, f0
|
||
fmr f20, f0
|
||
fmr f21, f0
|
||
fmr f22, f0
|
||
fmr f23, f0
|
||
fmr f24, f0
|
||
fmr f25, f0
|
||
fmr f26, f0
|
||
fmr f27, f0
|
||
fmr f28, f0
|
||
fmr f29, f0
|
||
fmr f30, f0
|
||
fmr f31, f0
|
||
|
||
|
||
mtfsfi 0, 0 /* initialize bit positons in FPSCR */
|
||
mtfsfi 1, 0
|
||
mtfsfi 2, 0
|
||
mtfsfi 3, 0
|
||
mtfsfi 4, 0
|
||
mtfsfi 5, 0
|
||
mtfsfi 6, 0
|
||
mtfsfi 7, 0
|
||
|
||
|
||
CLRBITS r30, r29, MSR_FP /* disable FPU and FPU exceptions */
|
||
mtmsr r30
|
||
|
||
blr
|
||
|
||
SPRG_init: /* initialize registers */
|
||
xor r30, r30, r30
|
||
|
||
mtspr XER, r30
|
||
mtspr CTR, r30
|
||
mtspr DSISR, r30
|
||
mtspr DAR, r30
|
||
mtspr DEC, r30
|
||
mtspr SDR1, r30
|
||
mtspr SRR0, r30
|
||
mtspr SRR1, r30
|
||
mtspr CSSR0, r30
|
||
mtspr CSSR1, r30
|
||
mtspr SPRG0, r30
|
||
mtspr SPRG1, r30
|
||
mtspr SPRG2, r30
|
||
mtspr SPRG3, r30
|
||
mtspr SPRG4, r30
|
||
mtspr SPRG5, r30
|
||
mtspr SPRG6, r30
|
||
mtspr SPRG7, r30
|
||
mtspr EAR, r30
|
||
mtspr TBWU, r30
|
||
mtspr TBWL, r30
|
||
mtspr IBAT0U, r30
|
||
mtspr IBAT0L, r30
|
||
mtspr IBAT1U, r30
|
||
mtspr IBAT1L, r30
|
||
mtspr IBAT2U, r30
|
||
mtspr IBAT2L, r30
|
||
mtspr IBAT3U, r30
|
||
mtspr IBAT3L, r30
|
||
mtspr IBAT4U, r30
|
||
mtspr IBAT4L, r30
|
||
mtspr IBAT5U, r30
|
||
mtspr IBAT5L, r30
|
||
mtspr IBAT6U, r30
|
||
mtspr IBAT6L, r30
|
||
mtspr IBAT7U, r30
|
||
mtspr IBAT7L, r30
|
||
mtspr DBAT0U, r30
|
||
mtspr DBAT0L, r30
|
||
mtspr DBAT1U, r30
|
||
mtspr DBAT1L, r30
|
||
mtspr DBAT2U, r30
|
||
mtspr DBAT2L, r30
|
||
mtspr DBAT3U, r30
|
||
mtspr DBAT3L, r30
|
||
mtspr DBAT4U, r30
|
||
mtspr DBAT4L, r30
|
||
mtspr DBAT5U, r30
|
||
mtspr DBAT5L, r30
|
||
mtspr DBAT6U, r30
|
||
mtspr DBAT6L, r30
|
||
mtspr DBAT7U, r30
|
||
mtspr DBAT7L, r30
|
||
mtspr DMISS, r30
|
||
mtspr DCMP, r30
|
||
mtspr HASH1, r30
|
||
mtspr HASH2, r30
|
||
mtspr IMISS, r30
|
||
mtspr ICMP, r30
|
||
mtspr RPA, r30
|
||
mtsr SR0, r30
|
||
mtsr SR1, r30
|
||
mtsr SR2, r30
|
||
mtsr SR3, r30
|
||
mtsr SR4, r30
|
||
mtsr SR5, r30
|
||
mtsr SR6, r30
|
||
mtsr SR7, r30
|
||
mtsr SR8, r30
|
||
mtsr SR9, r30
|
||
mtsr SR10, r30
|
||
mtsr SR12, r30
|
||
mtsr SR13, r30
|
||
mtsr SR14, r30
|
||
mtsr SR15, r30
|
||
|
||
|
||
|
||
|
||
|
||
blr
|
||
|
||
SPRG_brk_init:
|
||
xor r30, r30, r30
|
||
|
||
mtspr DABR2, r30
|
||
mtspr DBCR, r30
|
||
mtspr IBCR, r30
|
||
mtspr IABR, r30
|
||
mtspr HID2, r30
|
||
mtspr DABR, r30
|
||
mtspr IABR2, r30
|
||
|
||
|
||
|
||
|
||
blr
|
||
|
||
|
||
PPC_HID0_rd: /* get HID0 content to r30 */
|
||
|
||
|
||
mfspr r30, HID0
|
||
|
||
blr
|
||
|
||
|
||
PPC_HID0_wr: /* put r30 content to HID0 */
|
||
|
||
|
||
mtspr HID0, r30
|
||
|
||
blr
|
||
|
||
clr_mem:
|
||
mr r28, r29
|
||
srwi r29, r29, 2
|
||
mtctr r29 /* set ctr reg */
|
||
|
||
|
||
slwi r29, r29, 2
|
||
sub r28, r28, r29 /* maybe some residual bytes */
|
||
xor r29, r29, r29
|
||
|
||
|
||
clr_mem_word:
|
||
stswi r29, r30, 0x04 /* store r29 (word) to r30 memory location */
|
||
addi r30, r30, 0x04 /* increment r30 */
|
||
|
||
bdnz clr_mem_word /* dec counter and loop */
|
||
|
||
|
||
cmpwi r28, 0x00 /* clear mem. finished ? */
|
||
beq clr_mem_end;
|
||
mtctr r28 /* reload counter for residual bytes */
|
||
clr_mem_byte:
|
||
stswi r29, r30, 0x01 /* store r29 (byte) to r30 memory location */
|
||
addi r30, r30, 0x01 /* update r30 */
|
||
|
||
bdnz clr_mem_byte /* dec counter and loop */
|
||
|
||
clr_mem_end:
|
||
blr /* return */
|
||
|
||
|
||
|