forked from Imagelibrary/rtems
176 lines
3.9 KiB
C
176 lines
3.9 KiB
C
/*
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* Copyright (c) 2013 embedded brains GmbH. All rights reserved.
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*
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* embedded brains GmbH
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* Obere Lagerstr. 30
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* 82178 Puchheim
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* Germany
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* <rtems@embedded-brains.de>
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.com/license/LICENSE.
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*/
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#include <assert.h>
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#include <rtems/bspsmp.h>
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#include <libcpu/powerpc-utility.h>
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#include <bsp.h>
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#include <bsp/mmu.h>
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#include <bsp/qoriq.h>
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#include <bsp/vectors.h>
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#include <bsp/irq-generic.h>
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#include <bsp/linker-symbols.h>
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LINKER_SYMBOL(bsp_exc_vector_base);
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void _start_core_1(void);
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#define CORE_COUNT 2
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#define ONE_CORE(core) (1 << (core))
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#define ALL_CORES ((1 << CORE_COUNT) - 1)
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#define IPI_INDEX 0
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#define TLB_BEGIN 8
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#define TLB_END 16
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#define TLB_COUNT (TLB_END - TLB_BEGIN)
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/*
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* These values can be obtained with the debugger or a look into the
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* U-Boot sources (arch/powerpc/cpu/mpc85xx/release.S).
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*/
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#if 1
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#define BOOT_BEGIN 0x1fff0000
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#define BOOT_LAST 0x1fffffff
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#define SPIN_TABLE (BOOT_BEGIN + 0xf2a0)
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#else
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#define BOOT_BEGIN 0x3fff0000
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#define BOOT_LAST 0x3fffffff
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#define SPIN_TABLE (BOOT_BEGIN + 0xf240)
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#endif
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#define TLB_BEGIN 8
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#define TLB_END 16
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#define TLB_COUNT (TLB_END - TLB_BEGIN)
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typedef struct {
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uint32_t addr_upper;
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uint32_t addr_lower;
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uint32_t r3_upper;
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uint32_t r3_lower;
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uint32_t reserved;
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uint32_t pir;
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uint32_t r6_upper;
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uint32_t r6_lower;
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} uboot_spin_table;
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static uint32_t initial_core_1_stack[4096 / sizeof(uint32_t)];
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static void mmu_config_undo(void)
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{
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int i = 0;
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for (i = TLB_BEGIN; i < TLB_END; ++i) {
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qoriq_tlb1_invalidate(i);
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}
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}
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static void release_core_1(void)
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{
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uboot_spin_table *spin_table = (uboot_spin_table *) SPIN_TABLE;
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qoriq_mmu_context mmu_context;
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qoriq_mmu_context_init(&mmu_context);
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qoriq_mmu_add(&mmu_context, BOOT_BEGIN, BOOT_LAST, 0, 0, FSL_EIS_MAS3_SR | FSL_EIS_MAS3_SW);
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qoriq_mmu_partition(&mmu_context, TLB_COUNT);
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qoriq_mmu_write_to_tlb1(&mmu_context, TLB_BEGIN);
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spin_table->pir = 1;
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spin_table->r3_lower = (uint32_t) _Per_CPU_Information[1].interrupt_stack_high;
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spin_table->addr_upper = 0;
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rtems_cache_flush_multiple_data_lines(spin_table, sizeof(*spin_table));
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ppc_synchronize_data();
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spin_table->addr_lower = (uint32_t) _start_core_1;
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rtems_cache_flush_multiple_data_lines(spin_table, sizeof(*spin_table));
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mmu_config_undo();
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}
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void qoriq_secondary_cpu_initialize(void)
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{
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/* Disable decrementer */
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PPC_CLEAR_SPECIAL_PURPOSE_REGISTER_BITS(BOOKE_TCR, BOOKE_TCR_DIE);
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/* Initialize exception handler */
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ppc_exc_initialize_with_vector_base(
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PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
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(uintptr_t) _Per_CPU_Information[1].interrupt_stack_low,
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rtems_configuration_get_interrupt_stack_size(),
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bsp_exc_vector_base
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);
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/* Now it is possible to make the code execute only */
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qoriq_mmu_change_perm(
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FSL_EIS_MAS3_SR | FSL_EIS_MAS3_SX,
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FSL_EIS_MAS3_SX,
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FSL_EIS_MAS3_SR
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);
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/* Initialize interrupt support */
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bsp_interrupt_facility_initialize();
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bsp_interrupt_vector_enable(QORIQ_IRQ_IPI_0);
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rtems_smp_secondary_cpu_initialize();
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}
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static void ipi_handler(void *arg)
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{
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rtems_smp_process_interrupt();
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}
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uint32_t bsp_smp_initialize(uint32_t configured_cpu_count)
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{
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rtems_status_code sc;
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uint32_t cores = configured_cpu_count < CORE_COUNT ?
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configured_cpu_count : CORE_COUNT;
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sc = rtems_interrupt_handler_install(
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QORIQ_IRQ_IPI_0,
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"IPI",
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RTEMS_INTERRUPT_UNIQUE,
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ipi_handler,
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NULL
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);
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assert(sc == RTEMS_SUCCESSFUL);
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if (cores > 1) {
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release_core_1();
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}
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return cores;
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}
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void bsp_smp_broadcast_interrupt(void)
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{
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uint32_t self = ppc_processor_id();
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qoriq.pic.per_cpu [self].ipidr [IPI_INDEX].reg = ALL_CORES;
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}
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void _CPU_SMP_Send_interrupt(uint32_t target_processor_index)
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{
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uint32_t self = ppc_processor_id();
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qoriq.pic.per_cpu [self].ipidr [IPI_INDEX].reg =
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ONE_CORE(target_processor_index);
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}
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