forked from Imagelibrary/rtems
9b4422a251
Script does what is expected and tries to do it as smartly as possible. + remove occurrences of two blank comment lines next to each other after Id string line removed. + remove entire comment blocks which only exited to contain CVS Ids + If the processing left a blank line at the top of a file, it was removed.
255 lines
7.3 KiB
C
255 lines
7.3 KiB
C
/**
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* @file
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*
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* Mips CPU Dependent Source
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*
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* 2002: Greg Menke (gregory.menke@gsfc.nasa.gov)
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* Overhauled interrupt level and interrupt enable/disable code
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* to more exactly support MIPS. Our mods were for MIPS1 processors
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* MIPS3 ports are affected, though apps written to the old behavior
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* should still work OK.
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*
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* Conversion to MIPS port by Alan Cudmore <alanc@linuxstart.com> and
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* Joel Sherrill <joel@OARcorp.com>.
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*
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* These changes made the code conditional on standard cpp predefines,
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* merged the mips1 and mips3 code sequences as much as possible,
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* and moved some of the assembly code to C. Alan did much of the
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* initial analysis and rework. Joel took over from there and
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* wrote the JMR3904 BSP so this could be tested. Joel also
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* added the new interrupt vectoring support in libcpu and
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* tried to better support the various interrupt controllers.
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*/
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/*
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* Original MIP64ORION port by Craig Lebakken <craigl@transition.com>
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* COPYRIGHT (c) 1996 by Transition Networks Inc.
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*
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* To anyone who acknowledges that this file is provided "AS IS"
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* without any express or implied warranty:
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* permission to use, copy, modify, and distribute this file
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* for any purpose is hereby granted without fee, provided that
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* the above copyright notice and this notice appears in all
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* copies, and that the name of Transition Networks not be used in
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* advertising or publicity pertaining to distribution of the
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* software without specific, written prior permission.
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* Transition Networks makes no representations about the
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* suitability of this software for any purpose.
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*
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* COPYRIGHT (c) 1989-2012.
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* On-Line Applications Research Corporation (OAR).
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.com/license/LICENSE.
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*/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include <rtems/system.h>
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#include <rtems/score/isr.h>
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#include <rtems/score/wkspace.h>
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/*
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** Exception stack frame pointer used in cpu_asm to pass the exception stack frame
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** address to the context switch code.
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*/
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#if (__mips == 1) || (__mips == 32)
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typedef uint32_t ESF_PTR_TYPE;
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#elif (__mips == 3)
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typedef uint64_t ESF_PTR_TYPE;
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#else
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#error "unknown MIPS ISA"
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#endif
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ESF_PTR_TYPE __exceptionStackFrame = 0;
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/* _CPU_Initialize
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*
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* This routine performs processor dependent initialization.
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*
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* thread_dispatch - address of dispatching routine
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*/
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void _CPU_Initialize(void)
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{
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/*
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* If there is not an easy way to initialize the FP context
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* during Context_Initialize, then it is usually easier to
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* save an "uninitialized" FP context here and copy it to
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* the task's during Context_Initialize.
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*/
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#if CPU_HARDWARE_FP
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/* FP context initialization support goes here */
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_CPU_Null_fp_context.fpcs = 0x1000000; /* Set FS flag in floating point coprocessor
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control register to prevent underflow and
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inexact exceptions */
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#endif
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}
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/*
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* _CPU_ISR_Get_level
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*
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* This routine returns the current interrupt level.
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*/
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uint32_t _CPU_ISR_Get_level( void )
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{
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unsigned int sr;
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mips_get_sr(sr);
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/* printf("current sr=%08X, ",sr); */
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#if (__mips == 3) || (__mips == 32)
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/* IE bit and shift down hardware ints into bits 1 thru 6 */
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sr = (sr & SR_IE) | ((sr & mips_interrupt_mask()) >> 9);
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#elif __mips == 1
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/* IEC bit and shift down hardware ints into bits 1 thru 6 */
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sr = (sr & SR_IEC) | ((sr & mips_interrupt_mask()) >> 9);
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#else
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#error "CPU ISR level: unknown MIPS level for SR handling"
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#endif
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return sr;
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}
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void _CPU_ISR_Set_level( uint32_t new_level )
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{
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unsigned int sr, srbits;
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/*
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** mask off the int level bits only so we can
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** preserve software int settings and FP enable
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** for this thread. Note we don't force software ints
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** enabled when changing level, they were turned on
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** when this task was created, but may have been turned
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** off since, so we'll just leave them alone.
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*/
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new_level &= 0xff;
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mips_get_sr(sr);
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#if (__mips == 3) || (__mips == 32)
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mips_set_sr( (sr & ~SR_IE) ); /* first disable ie bit (recommended) */
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srbits = sr & ~(0xfc00 | SR_IE);
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sr = srbits | ((new_level==0)? (mips_interrupt_mask() | SR_IE): \
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(((new_level<<9) & mips_interrupt_mask()) | \
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((new_level & 1)?SR_IE:0)));
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/*
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if ( (new_level & SR_EXL) == (sr & SR_EXL) )
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return;
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if ( (new_level & SR_EXL) == 0 ) {
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sr &= ~SR_EXL; * clear the EXL bit *
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mips_set_sr(sr);
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} else {
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sr |= SR_EXL|SR_IE; * enable exception level *
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mips_set_sr(sr); * first disable ie bit (recommended) *
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}
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*/
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#elif __mips == 1
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mips_set_sr( (sr & ~SR_IEC) );
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srbits = sr & ~(0xfc00 | SR_IEC);
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sr = srbits | ((new_level==0)?0xfc01:( ((new_level<<9) & 0xfc00) | \
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(new_level & SR_IEC)));
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#else
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#error "CPU ISR level: unknown MIPS level for SR handling"
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#endif
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mips_set_sr( sr );
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}
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/*
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* _CPU_Install_interrupt_stack
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*/
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void _CPU_Install_interrupt_stack( void )
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{
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/* we don't support this yet */
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}
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/*
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* _CPU_Context_Initialize
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*
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* This kernel routine initializes the basic non-FP context area associated
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* with each thread.
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*
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* Input parameters:
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* the_context - pointer to the context area
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* stack_base - address of memory for the SPARC
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* size - size in bytes of the stack area
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* new_level - interrupt level for this context area
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* entry_point - the starting execution point for this this context
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* is_fp - TRUE if this context is associated with an FP thread
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*
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* Output parameters: NONE
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*/
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void _CPU_Context_Initialize(
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Context_Control *the_context,
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uintptr_t *stack_base,
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uint32_t size,
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uint32_t new_level,
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void *entry_point,
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bool is_fp
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)
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{
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uintptr_t stack_tmp;
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__MIPS_REGISTER_TYPE intlvl = new_level & 0xff;
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stack_tmp = (uintptr_t)stack_base;
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stack_tmp += ((size) - CPU_STACK_ALIGNMENT);
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stack_tmp &= (__MIPS_REGISTER_TYPE) ~(CPU_STACK_ALIGNMENT - 1);
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the_context->sp = (__MIPS_REGISTER_TYPE) stack_tmp;
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the_context->fp = (__MIPS_REGISTER_TYPE) stack_tmp;
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the_context->ra = (__MIPS_REGISTER_TYPE) (uintptr_t)entry_point;
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the_context->c0_sr =
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((intlvl==0)? (mips_interrupt_mask() | 0x300 | _INTON):
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( ((intlvl<<9) & mips_interrupt_mask()) | 0x300 |
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((intlvl & 1)?_INTON:0)) ) |
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SR_CU0 | ((is_fp)?SR_CU1:0) | _EXTRABITS;
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}
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/*
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* _CPU_Internal_threads_Idle_thread_body
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*
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* NOTES:
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*
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* 1. This is the same as the regular CPU independent algorithm.
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*
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* 2. If you implement this using a "halt", "idle", or "shutdown"
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* instruction, then don't forget to put it in an infinite loop.
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*
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* 3. Be warned. Some processors with onboard DMA have been known
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* to stop the DMA if the CPU were put in IDLE mode. This might
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* also be a problem with other on-chip peripherals. So use this
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* hook with caution.
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*/
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void *_CPU_Thread_Idle_body( uintptr_t ignored )
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{
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#if (__mips == 3) || (__mips == 32)
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for( ; ; )
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__asm__ volatile("wait"); /* use wait to enter low power mode */
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#elif __mips == 1
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for( ; ; )
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;
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#else
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#error "IDLE: __mips not set to 1 or 3"
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#endif
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}
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