forked from Imagelibrary/rtems
9b4422a251
Script does what is expected and tries to do it as smartly as possible. + remove occurrences of two blank comment lines next to each other after Id string line removed. + remove entire comment blocks which only exited to contain CVS Ids + If the processing left a blank line at the top of a file, it was removed.
123 lines
2.8 KiB
C
123 lines
2.8 KiB
C
/**
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* @file
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*
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* @ingroup ScoreCPU
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*
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* @brief ARM architecture support implementation.
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*/
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/*
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* COPYRIGHT (c) 2000 Canon Research Centre France SA.
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* Emmanuel Raguet, mailto:raguet@crf.canon.fr
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*
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* Copyright (c) 2002 Advent Networks, Inc
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* Jay Monkman <jmonkman@adventnetworks.com>
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*
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* Copyright (c) 2007 Ray xu <rayx.cn@gmail.com>
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*
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* Copyright (c) 2009-2011 embedded brains GmbH
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.com/license/LICENSE.
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*/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include <rtems/system.h>
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#include <rtems.h>
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#include <rtems/bspIo.h>
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#include <rtems/score/isr.h>
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#include <rtems/score/wkspace.h>
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#include <rtems/score/thread.h>
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#include <rtems/score/cpu.h>
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#ifdef ARM_MULTILIB_ARCH_V4
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/*
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* This variable can be used to change the running mode of the execution
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* contexts.
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*/
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uint32_t arm_cpu_mode = 0x13;
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void _CPU_Context_Initialize(
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Context_Control *the_context,
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void *stack_area_begin,
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size_t stack_area_size,
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uint32_t new_level,
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void (*entry_point)( void ),
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bool is_fp
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)
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{
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the_context->register_sp = (uint32_t) stack_area_begin + stack_area_size;
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the_context->register_lr = (uint32_t) entry_point;
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the_context->register_cpsr = new_level | arm_cpu_mode;
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}
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/* Preprocessor magic for stringification of x */
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#define _CPU_ISR_LEVEL_DO_STRINGOF( x) #x
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#define _CPU_ISR_LEVEL_STRINGOF( x) _CPU_ISR_LEVEL_DO_STRINGOF( x)
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void _CPU_ISR_Set_level( uint32_t level )
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{
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uint32_t arm_switch_reg;
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__asm__ volatile (
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ARM_SWITCH_TO_ARM
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"mrs %[arm_switch_reg], cpsr\n"
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"bic %[arm_switch_reg], #" _CPU_ISR_LEVEL_STRINGOF( CPU_MODES_INTERRUPT_MASK ) "\n"
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"orr %[arm_switch_reg], %[level]\n"
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"msr cpsr, %0\n"
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ARM_SWITCH_BACK
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: [arm_switch_reg] "=&r" (arm_switch_reg)
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: [level] "r" (level)
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);
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}
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uint32_t _CPU_ISR_Get_level( void )
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{
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ARM_SWITCH_REGISTERS;
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uint32_t level;
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__asm__ volatile (
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ARM_SWITCH_TO_ARM
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"mrs %[level], cpsr\n"
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"and %[level], #" _CPU_ISR_LEVEL_STRINGOF( CPU_MODES_INTERRUPT_MASK ) "\n"
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ARM_SWITCH_BACK
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: [level] "=&r" (level) ARM_SWITCH_ADDITIONAL_OUTPUT
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);
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return level;
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}
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void _CPU_ISR_install_vector(
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uint32_t vector,
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proc_ptr new_handler,
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proc_ptr *old_handler
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)
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{
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/* Redirection table starts at the end of the vector table */
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volatile uint32_t *table = (volatile uint32_t *) (MAX_EXCEPTIONS * 4);
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uint32_t current_handler = table [vector];
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/* The current handler is now the old one */
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if (old_handler != NULL) {
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*old_handler = (proc_ptr) current_handler;
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}
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/* Write only if necessary to avoid writes to a maybe read-only memory */
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if (current_handler != (uint32_t) new_handler) {
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table [vector] = (uint32_t) new_handler;
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}
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}
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void _CPU_Initialize( void )
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{
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/* Do nothing */
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}
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#endif /* ARM_MULTILIB_ARCH_V4 */
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