forked from Imagelibrary/rtems
91 lines
2.9 KiB
C
91 lines
2.9 KiB
C
/* SPDX-License-Identifier: BSD-2-Clause */
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/* PCI Access Library
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*
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* COPYRIGHT (c) 2010 Cobham Gaisler AB.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <pci.h>
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#include <pci/access.h>
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/* Access Routines valid after a PCI-Access-Driver has registered */
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struct pci_access_drv pci_access_ops;
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/* Read a 8-bit register over configuration space */
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int pci_cfg_r8(pci_dev_t dev, int ofs, uint8_t *data)
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{
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return pci_access_ops.cfg.read8(dev, ofs, data);
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}
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/* Read a 16-bit register over configuration space */
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int pci_cfg_r16(pci_dev_t dev, int ofs, uint16_t *data)
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{
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return pci_access_ops.cfg.read16(dev, ofs, data);
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}
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/* Read a 32-bit register over configuration space */
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int pci_cfg_r32(pci_dev_t dev, int ofs, uint32_t *data)
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{
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return pci_access_ops.cfg.read32(dev, ofs, data);
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}
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/* Write a 8-bit register over configuration space */
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int pci_cfg_w8(pci_dev_t dev, int ofs, uint8_t data)
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{
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return pci_access_ops.cfg.write8(dev, ofs, data);
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}
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/* Write a 16-bit register over configuration space */
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int pci_cfg_w16(pci_dev_t dev, int ofs, uint16_t data)
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{
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return pci_access_ops.cfg.write16(dev, ofs, data);
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}
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/* Write a 32-bit register over configuration space */
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int pci_cfg_w32(pci_dev_t dev, int ofs, uint32_t data)
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{
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return pci_access_ops.cfg.write32(dev, ofs, data);
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}
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void pci_modify_cmdsts(pci_dev_t dev, uint32_t mask, uint32_t val)
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{
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uint32_t data;
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pci_cfg_r32(dev, PCIR_COMMAND, &data);
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data &= ~mask;
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data |= val;
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pci_cfg_w32(dev, PCIR_COMMAND, data);
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}
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/* Register a driver for handling access to PCI */
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int pci_access_drv_register(struct pci_access_drv *drv)
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{
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if (pci_access_ops.cfg.read8)
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return -1; /* Already registered a driver.. */
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pci_access_ops = *drv;
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return 0;
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}
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