forked from Imagelibrary/rtems
82 lines
2.1 KiB
C
82 lines
2.1 KiB
C
/**
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* @file
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*
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* Common Code for Vectoring MIPS Exceptions
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*
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* The actual decoding of the cause register and vector number assignment
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* is CPU model specific.
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*/
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/*
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* COPYRIGHT (c) 1989-2012.
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* On-Line Applications Research Corporation (OAR).
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#include <rtems.h>
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#include <inttypes.h>
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#include <stdlib.h>
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#include <string.h>
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#include <rtems/mips/iregdef.h>
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#include <rtems/mips/idtcpu.h>
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#include <rtems/bspIo.h>
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#include <bsp/irq-generic.h>
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struct regdef
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{
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int offset;
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char *name;
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};
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static const struct regdef dumpregs[]= {
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{ R_RA, "R_RA" }, { R_V0, "R_V0" }, { R_V1, "R_V1" },
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{ R_A0, "R_A0" }, { R_A1, "R_A1" }, { R_A2, "R_A2" },
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{ R_A3, "R_A3" }, { R_T0, "R_T0" }, { R_T1, "R_T1" },
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{ R_T2, "R_T2" }, { R_T3, "R_T3" }, { R_T4, "R_T4" },
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{ R_T5, "R_T5" }, { R_T6, "R_T6" }, { R_T7, "R_T7" },
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{ R_T8, "R_T8" }, { R_MDLO, "R_MDLO" }, { R_MDHI, "R_MDHI" },
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{ R_GP, "R_GP" }, { R_FP, "R_FP" }, { R_AT, "R_AT" },
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{ R_EPC,"R_EPC"}, { -1, NULL }
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};
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void _CPU_Exception_frame_print( const CPU_Exception_frame *frame )
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{
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uint32_t *frame_u32;
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int i, j;
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frame_u32 = (uint32_t *)frame;
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for(i=0; dumpregs[i].offset > -1; i++)
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{
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printk(" %s", dumpregs[i].name);
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for(j=0; j< 7-strlen(dumpregs[i].name); j++) printk(" ");
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#if (__mips == 1 ) || (__mips == 32)
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printk(" %08" PRIu32 "%c",
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frame_u32[dumpregs[i].offset], (i%3) ? '\t' : '\n' );
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#elif __mips == 3
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printk(" %08" PRIu32 "", frame_u32[2 * dumpregs[i].offset + 1] );
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printk("%08" PRIu32 "%c",
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frame_u32[2 * dumpregs[i].offset], (i%2) ? '\t' : '\n' );
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#endif
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}
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printk( "\n" );
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}
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/*
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* There are constants defined for these but they should basically
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* all be close to the same set.
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*/
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void mips_vector_exceptions( CPU_Interrupt_frame *frame )
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{
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uint32_t cause;
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uint32_t exc;
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mips_get_cause( cause );
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exc = (cause >> 2) & 0x1f;
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bsp_interrupt_handler_dispatch( exc );
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}
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