forked from Imagelibrary/rtems
127 lines
5.1 KiB
C
127 lines
5.1 KiB
C
/* SPDX-License-Identifier: BSD-2-Clause */
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/**
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* @file
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*
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* MIPS Tx4925 specific information
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*/
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/*
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* COPYRIGHT (c) 1989-2012.
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* On-Line Applications Research Corporation (OAR).
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __TX4925_h
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#define __TX4925_h
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#define TX4925_REG_BASE 0xFF1F0000
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/*
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* Configuration Registers
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*/
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#define TX4925_CFG_CCFG 0xE000 /* Chip Configuration Register */
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#define TX4925_CFG_REVID 0xE004 /* Chip Revision ID Register */
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#define TX4925_CFG_PCFG 0xE008 /* Pin Configuration Register */
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#define TX4925_CFG_TOEA 0xE00C /* TimeOut Error Access Address Register */
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#define TX4925_CFG_PDNCTR 0xE010 /* Power Down Control Register */
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#define TX4925_CFG_GARBP 0xE018 /* GBUS Arbiter Priority Register */
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#define TX4925_CFG_TOCNT 0xE020 /* Timeout Count Register */
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#define TX4925_CFG_DRQCTR 0xE024 /* DMA Request Control Register */
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#define TX4925_CFG_CLKCTR 0xE028 /* Clock Control Register */
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#define TX4925_CFG_GARBC 0xE02C /* GBUS Arbiter Control Register */
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#define TX4925_CFG_RAMP 0xE030 /* Register Address Mapping Register */
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/* Pin Configuration register bits */
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#define SELCHI 0x00100000
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#define SELTMR0 0x00000200
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/*
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* Timer Registers
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*/
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#define TX4925_TIMER0_BASE 0xF000
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#define TX4925_TIMER1_BASE 0xF100
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#define TX4925_TIMER2_BASE 0xF200
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#define TX4925_TIMER_TCR 0x00 /* Timer Control Register */
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#define TX4925_TIMER_TISR 0x04 /* Timer Interrupt Status Register */
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#define TX4925_TIMER_CPRA 0x08 /* Compare Register A */
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#define TX4925_TIMER_CPRB 0x0C /* Compare Register B */
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#define TX4925_TIMER_ITMR 0x10 /* Interval Timer Mode Register */
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#define TX4925_TIMER_CCDR 0x20 /* Divide Cycle Register */
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#define TX4925_TIMER_PGMR 0x30 /* Pulse Generator Mode Register */
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#define TX4925_TIMER_WTMR 0x40 /* Reserved Register */
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#define TX4925_TIMER_TRR 0xF0 /* Timer Read Register */
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/* ITMR register bits */
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#define TIMER_CLEAR_ENABLE_MASK 0x1
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#define TIMER_INT_ENABLE_MASK 0x8000
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/* PGMR register bits */
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#define FFI 0x1
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#define TPIAE 0x4000
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#define TPIBE 0x8000
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/* TISR register bits */
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#define TIIS 0x1
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#define TPIAS 0x2
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#define TPIBS 0x4
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#define TWIS 0x8
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/*
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* Interrupt Controller Registers
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*/
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#define TX4925_IRQCTL_DEN 0xF600 /* Interrupt Detection Enable Register */
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#define TX4925_IRQCTL_DM0 0xF604 /* Interrupt Detection Mode Register 0 */
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#define TX4925_IRQCTL_DM1 0xF608 /* Interrupt Detection Mode Register 1 */
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#define TX4925_IRQCTL_LVL0 0xF610 /* Interrupt Level Register 0 */
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#define TX4925_IRQCTL_LVL1 0xF614 /* Interrupt Level Register 1 */
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#define TX4925_IRQCTL_LVL2 0xF618 /* Interrupt Level Register 2 */
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#define TX4925_IRQCTL_LVL3 0xF61C /* Interrupt Level Register 3 */
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#define TX4925_IRQCTL_LVL4 0xF620 /* Interrupt Level Register 4 */
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#define TX4925_IRQCTL_LVL5 0xF624 /* Interrupt Level Register 5 */
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#define TX4925_IRQCTL_LVL6 0xF628 /* Interrupt Level Register 6 */
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#define TX4925_IRQCTL_LVL7 0xF62C /* Interrupt Level Register 7 */
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#define TX4925_IRQCTL_MSK 0xF640 /* Interrupt Mask Register */
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#define TX4925_IRQCTL_EDC 0xF660 /* Interrupt Edge Detection Clear Register */
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#define TX4925_IRQCTL_PND 0xF680 /* Interrupt Pending Register */
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#define TX4925_IRQCTL_CS 0xF6A0 /* Interrupt Current Status Register */
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#define TX4925_IRQCTL_FLAG0 0xF510 /* Interrupt Request Flag Register 0 */
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#define TX4925_IRQCTL_FLAG1 0xF514 /* Interrupt Request Flag Register 1 */
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#define TX4925_IRQCTL_POL 0xF518 /* Interrupt Request Polarity Control Register */
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#define TX4925_IRQCTL_RCNT 0xF51C /* Interrupt Request Control Register */
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#define TX4925_IRQCTL_MASKINT 0xF520 /* Interrupt Request Internal Interrupt Mask Register */
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#define TX4925_IRQCTL_MASKEXT 0xF524 /* Interrupt Request External Interrupt Mask Register */
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#define TX4925_REG_READ( _base, _register ) \
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*((volatile uint32_t *)((_base) + (_register)))
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#define TX4925_REG_WRITE( _base, _register, _value ) \
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*((volatile uint32_t *)((_base) + (_register))) = (_value)
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#endif
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