forked from Imagelibrary/rtems
c03e2bc8c7
* cpu.c, rtems/score/cpu.h: Eliminate _CPU_Thread_dispatch_pointer and passing address of _Thread_Dispatch to _CPU_Initialize. Clean up comments.
333 lines
9.1 KiB
C
333 lines
9.1 KiB
C
/*
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* SPARC Dependent Source
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*
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* COPYRIGHT (c) 1989-2007.
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* On-Line Applications Research Corporation (OAR).
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.com/license/LICENSE.
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*
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* $Id$
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*/
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#include <rtems/system.h>
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#include <rtems/score/isr.h>
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#include <rtems/rtems/cache.h>
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/*
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* This initializes the set of opcodes placed in each trap
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* table entry. The routine which installs a handler is responsible
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* for filling in the fields for the _handler address and the _vector
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* trap type.
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*
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* The constants following this structure are masks for the fields which
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* must be filled in when the handler is installed.
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*/
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const CPU_Trap_table_entry _CPU_Trap_slot_template = {
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0xa1480000, /* mov %psr, %l0 */
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0x29000000, /* sethi %hi(_handler), %l4 */
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0x81c52000, /* jmp %l4 + %lo(_handler) */
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0xa6102000 /* mov _vector, %l3 */
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};
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/*PAGE
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*
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* _CPU_Initialize
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*
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* This routine performs processor dependent initialization.
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*
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* INPUT PARAMETERS: NONE
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*
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* Output Parameters: NONE
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*
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* NOTE: There is no need to save the pointer to the thread dispatch routine.
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* The SPARC's assembly code can reference it directly with no problems.
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*/
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void _CPU_Initialize(void)
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{
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#if (SPARC_HAS_FPU == 1)
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Context_Control_fp *pointer;
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/*
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* This seems to be the most appropriate way to obtain an initial
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* FP context on the SPARC. The NULL fp context is copied it to
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* the task's FP context during Context_Initialize.
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*/
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pointer = &_CPU_Null_fp_context;
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_CPU_Context_save_fp( &pointer );
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#endif
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/*
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* Since no tasks have been created yet and no interrupts have occurred,
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* there is no way that the currently executing thread can have an
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* _ISR_Dispatch stack frame on its stack.
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*/
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_CPU_ISR_Dispatch_disable = 0;
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}
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/*PAGE
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*
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* _CPU_ISR_Get_level
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*
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* Input Parameters: NONE
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*
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* Output Parameters:
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* returns the current interrupt level (PIL field of the PSR)
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*/
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uint32_t _CPU_ISR_Get_level( void )
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{
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uint32_t level;
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sparc_get_interrupt_level( level );
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return level;
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}
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/*PAGE
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*
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* _CPU_ISR_install_raw_handler
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*
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* This routine installs the specified handler as a "raw" non-executive
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* supported trap handler (a.k.a. interrupt service routine).
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*
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* Input Parameters:
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* vector - trap table entry number plus synchronous
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* vs. asynchronous information
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* new_handler - address of the handler to be installed
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* old_handler - pointer to an address of the handler previously installed
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*
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* Output Parameters: NONE
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* *new_handler - address of the handler previously installed
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*
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* NOTE:
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*
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* On the SPARC, there are really only 256 vectors. However, the executive
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* has no easy, fast, reliable way to determine which traps are synchronous
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* and which are asynchronous. By default, synchronous traps return to the
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* instruction which caused the interrupt. So if you install a software
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* trap handler as an executive interrupt handler (which is desirable since
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* RTEMS takes care of window and register issues), then the executive needs
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* to know that the return address is to the trap rather than the instruction
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* following the trap.
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*
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* So vectors 0 through 255 are treated as regular asynchronous traps which
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* provide the "correct" return address. Vectors 256 through 512 are assumed
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* by the executive to be synchronous and to require that the return address
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* be fudged.
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*
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* If you use this mechanism to install a trap handler which must reexecute
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* the instruction which caused the trap, then it should be installed as
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* an asynchronous trap. This will avoid the executive changing the return
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* address.
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*/
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void _CPU_ISR_install_raw_handler(
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uint32_t vector,
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proc_ptr new_handler,
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proc_ptr *old_handler
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)
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{
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uint32_t real_vector;
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CPU_Trap_table_entry *tbr;
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CPU_Trap_table_entry *slot;
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uint32_t u32_tbr;
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uint32_t u32_handler;
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/*
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* Get the "real" trap number for this vector ignoring the synchronous
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* versus asynchronous indicator included with our vector numbers.
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*/
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real_vector = SPARC_REAL_TRAP_NUMBER( vector );
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/*
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* Get the current base address of the trap table and calculate a pointer
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* to the slot we are interested in.
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*/
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sparc_get_tbr( u32_tbr );
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u32_tbr &= 0xfffff000;
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tbr = (CPU_Trap_table_entry *) u32_tbr;
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slot = &tbr[ real_vector ];
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/*
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* Get the address of the old_handler from the trap table.
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*
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* NOTE: The old_handler returned will be bogus if it does not follow
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* the RTEMS model.
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*/
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#define HIGH_BITS_MASK 0xFFFFFC00
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#define HIGH_BITS_SHIFT 10
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#define LOW_BITS_MASK 0x000003FF
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if ( slot->mov_psr_l0 == _CPU_Trap_slot_template.mov_psr_l0 ) {
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u32_handler =
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(slot->sethi_of_handler_to_l4 << HIGH_BITS_SHIFT) |
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(slot->jmp_to_low_of_handler_plus_l4 & LOW_BITS_MASK);
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*old_handler = (proc_ptr) u32_handler;
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} else
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*old_handler = 0;
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/*
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* Copy the template to the slot and then fix it.
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*/
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*slot = _CPU_Trap_slot_template;
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u32_handler = (uint32_t) new_handler;
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slot->mov_vector_l3 |= vector;
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slot->sethi_of_handler_to_l4 |=
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(u32_handler & HIGH_BITS_MASK) >> HIGH_BITS_SHIFT;
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slot->jmp_to_low_of_handler_plus_l4 |= (u32_handler & LOW_BITS_MASK);
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/* need to flush icache after this !!! */
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rtems_cache_invalidate_entire_instruction();
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}
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/*PAGE
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*
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* _CPU_ISR_install_vector
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*
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* This kernel routine installs the RTEMS handler for the
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* specified vector.
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*
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* Input parameters:
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* vector - interrupt vector number
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* new_handler - replacement ISR for this vector number
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* old_handler - pointer to former ISR for this vector number
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*
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* Output parameters:
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* *old_handler - former ISR for this vector number
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*
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*/
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void _CPU_ISR_install_vector(
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uint32_t vector,
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proc_ptr new_handler,
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proc_ptr *old_handler
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)
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{
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uint32_t real_vector;
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proc_ptr ignored;
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/*
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* Get the "real" trap number for this vector ignoring the synchronous
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* versus asynchronous indicator included with our vector numbers.
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*/
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real_vector = SPARC_REAL_TRAP_NUMBER( vector );
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/*
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* Return the previous ISR handler.
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*/
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*old_handler = _ISR_Vector_table[ real_vector ];
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/*
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* Install the wrapper so this ISR can be invoked properly.
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*/
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_CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored );
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/*
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* We put the actual user ISR address in '_ISR_vector_table'. This will
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* be used by the _ISR_Handler so the user gets control.
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*/
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_ISR_Vector_table[ real_vector ] = new_handler;
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}
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/*PAGE
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*
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* _CPU_Context_Initialize
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*
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* This kernel routine initializes the basic non-FP context area associated
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* with each thread.
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*
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* Input parameters:
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* the_context - pointer to the context area
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* stack_base - address of memory for the SPARC
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* size - size in bytes of the stack area
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* new_level - interrupt level for this context area
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* entry_point - the starting execution point for this this context
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* is_fp - TRUE if this context is associated with an FP thread
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*
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* Output parameters: NONE
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*/
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void _CPU_Context_Initialize(
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Context_Control *the_context,
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uint32_t *stack_base,
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uint32_t size,
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uint32_t new_level,
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void *entry_point,
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bool is_fp
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)
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{
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uint32_t stack_high; /* highest "stack aligned" address */
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uint32_t the_size;
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uint32_t tmp_psr;
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/*
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* On CPUs with stacks which grow down (i.e. SPARC), we build the stack
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* based on the stack_high address.
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*/
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stack_high = ((uint32_t)(stack_base) + size);
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stack_high &= ~(CPU_STACK_ALIGNMENT - 1);
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the_size = size & ~(CPU_STACK_ALIGNMENT - 1);
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/*
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* See the README in this directory for a diagram of the stack.
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*/
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the_context->o7 = ((uint32_t) entry_point) - 8;
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the_context->o6_sp = stack_high - CPU_MINIMUM_STACK_FRAME_SIZE;
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the_context->i6_fp = 0;
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/*
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* Build the PSR for the task. Most everything can be 0 and the
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* CWP is corrected during the context switch.
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*
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* The EF bit determines if the floating point unit is available.
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* The FPU is ONLY enabled if the context is associated with an FP task
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* and this SPARC model has an FPU.
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*/
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sparc_get_psr( tmp_psr );
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tmp_psr &= ~SPARC_PSR_PIL_MASK;
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tmp_psr |= (new_level << 8) & SPARC_PSR_PIL_MASK;
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tmp_psr &= ~SPARC_PSR_EF_MASK; /* disabled by default */
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#if (SPARC_HAS_FPU == 1)
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/*
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* If this bit is not set, then a task gets a fault when it accesses
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* a floating point register. This is a nice way to detect floating
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* point tasks which are not currently declared as such.
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*/
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if ( is_fp )
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tmp_psr |= SPARC_PSR_EF_MASK;
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#endif
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the_context->psr = tmp_psr;
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/*
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* Since THIS thread is being created, there is no way that THIS
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* thread can have an _ISR_Dispatch stack frame on its stack.
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*/
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the_context->isr_dispatch_disable = 0;
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}
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