forked from Imagelibrary/rtems
bfc76f9e1b
PR 1599/cpukit * cpu_asm.S: Rename _Context_Switch_necessary to _Thread_Dispatch_necessary to more properly reflect the intent.
462 lines
10 KiB
ArmAsm
462 lines
10 KiB
ArmAsm
/* cpu_asm.c ===> cpu_asm.S or cpu_asm.s
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*
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* This file contains the basic algorithms for all assembly code used
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* in an specific CPU port of RTEMS. These algorithms must be implemented
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* in assembly language
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*
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* NOTE: This is supposed to be a .S or .s file NOT a C file.
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*
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* COPYRIGHT (c) 1989-2008.
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* On-Line Applications Research Corporation (OAR).
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.com/license/LICENSE.
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*
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* $Id$
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*/
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/*
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* This is supposed to be an assembly file. This means that system.h
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* and cpu.h should not be included in a "real" cpu_asm file. An
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* implementation in assembly should include "cpu_asm.h>
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*/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include <rtems/asm.h>
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#include <avr/sfr_defs.h>
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#include <rtems/score/percpu.h>
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#define jmpb_hi r25
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#define jmpb_lo r24
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#define val_hi r23
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#define val_lo r22
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#define ret_lo r24
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#define ret_hi r25
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PUBLIC( setjmp )
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SYM( setjmp ):
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X_movw XL, jmpb_lo
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/*;save call-saved registers and frame pointer*/
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.irp .L_regno, 2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,28,29
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st X+, r\.L_regno
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.endr
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/*;get return address*/
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pop ZH
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pop ZL
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/*save stack pointer (after popping)*/
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in ret_lo, AVR_STACK_POINTER_LO_ADDR
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st X+, ret_lo
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#ifdef _HAVE_AVR_STACK_POINTER_HI
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in ret_lo, AVR_STACK_POINTER_HI_ADDR
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st X+, ret_lo
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#else
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st X+, ret_lo
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#endif
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/*save status reg (I flag)*/
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in ret_lo, AVR_STATUS_ADDR
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st X+, ret_lo
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/*save return addr*/
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st X+, ZL
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st X+, ZH
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/*return zero*/
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clr ret_hi
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clr ret_lo
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ijmp
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.size _U(setjmp),.-_U(setjmp)
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.global _U(longjmp)
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.type _U(longjmp), @function
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_U(longjmp):
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X_movw XL, jmpb_lo
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/*return value*/
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X_movw ret_lo, val_lo
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/*if zero, change to 1*/
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cpi ret_lo, 1
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cpc ret_hi, __zero_reg__
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adc ret_lo, __zero_reg__
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/*restore call-saved registers and frame pointer*/
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.irp .L_regno, 2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,28,29
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ld r\.L_regno, X+
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.endr
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/*; restore stack pointer (SP value before the setjmp() call) and SREG*/
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ld ZL, X+
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ld ZH, X+
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ld __tmp_reg__, X+
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#if defined (__AVR_XMEGA__) && __AVR_XMEGA__
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/* A write to SPL will automatically disable interrupts for up to 4
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instructions or until the next I/O memory write. */
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out AVR_STATUS_ADDR, __tmp_reg__
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out AVR_STACK_POINTER_LO_ADDR, ZL
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out AVR_STACK_POINTER_HI_ADDR, ZH
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#else
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# ifdef _HAVE_AVR_STACK_POINTER_HI
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/* interrupts disabled for shortest possible time (3 cycles) */
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cli
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out AVR_STACK_POINTER_HI_ADDR, ZH
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# endif
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/* Restore status register (including the interrupt enable flag).
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Interrupts are re-enabled only after the next instruction. */
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out AVR_STATUS_ADDR, __tmp_reg__
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out AVR_STACK_POINTER_LO_ADDR, ZL
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#endif
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; get return address and jump
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ld ZL, X+
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ld ZH, X+
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#if defined(__AVR_3_BYTE_PC__) && __AVR_3_BYTE_PC__
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ld __tmp_reg__, X+
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.L_jmp3:
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push ZL
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push ZH
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push __tmp_reg__
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ret
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#else
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ijmp
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#endif
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.size _U(longjmp), . - _U(longjmp)
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/*
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* _CPU_Context_save_fp_context
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*
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* This routine is responsible for saving the FP context
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* at *fp_context_ptr. If the point to load the FP context
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* from is changed then the pointer is modified by this routine.
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*
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* Sometimes a macro implementation of this is in cpu.h which dereferences
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* the ** and a similarly named routine in this file is passed something
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* like a (Context_Control_fp *). The general rule on making this decision
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* is to avoid writing assembly language.
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*
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* NO_CPU Specific Information:
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*
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* XXX document implementation including references if appropriate
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void _CPU_Context_save_fp(
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Context_Control_fp **fp_context_ptr
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)
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{
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}
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*/
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PUBLIC(_CPU_Context_save_fp)
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SYM(_CPU_Context_save_fp):
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ret
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/*
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* _CPU_Context_restore_fp_context
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*
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* This routine is responsible for restoring the FP context
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* at *fp_context_ptr. If the point to load the FP context
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* from is changed then the pointer is modified by this routine.
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*
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* Sometimes a macro implementation of this is in cpu.h which dereferences
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* the ** and a similarly named routine in this file is passed something
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* like a (Context_Control_fp *). The general rule on making this decision
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* is to avoid writing assembly language.
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*
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* NO_CPU Specific Information:
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*
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* XXX document implementation including references if appropriate
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void _CPU_Context_restore_fp(
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Context_Control_fp **fp_context_ptr
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)
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{
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}
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*/
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PUBLIC(_CPU_Context_restore_fp)
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SYM(_CPU_Context_restore_fp):
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ret
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/* _CPU_Context_switch
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*
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* This routine performs a normal non-FP context switch.
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*
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* NO_CPU Specific Information:
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*
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* XXX document implementation including references if appropriate
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void _CPU_Context_switch(
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Context_Control *run,
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Context_Control *heir
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);
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*/
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PUBLIC(_CPU_Context_switch)
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SYM(_CPU_Context_switch):
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mov r26, r24 /*r26,r27 is X*/
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mov r27, r25
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mov r24, r22
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mov r25, r23
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/*save registers*/
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#if 1
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/*if this section is removed there is a problem.*/
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/*debug section start*/
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pop r22
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pop r23
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push r22
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push r23
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/*debug section end*/
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#endif
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push r2
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push r3
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push r4
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push r5
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push r6
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push r7
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push r8
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push r9
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push r10
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push r11
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push r12
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push r13
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push r14
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push r15
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push r16
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push r17
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push r28
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push r29
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/*load sreg*/
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lds r23,0x5f /*load sreg*/
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/*disable interrupts*/
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cli
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/*load stack pointer*/
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lds r22,0x5d /*spl*/
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lds r21,0x5e /*sph*/
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/*save sreg and sp to context struct*/
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/*save low then high byte --- verify this delete when verified*/
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st X+, r22
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st X+, r21
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st X, r23
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PUBLIC(_CPU_Context_restore)
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SYM(_CPU_Context_restore):
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mov r26,r24 /* R26/27 are X */
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mov r27,r25
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/*restore stack pointer*/
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ld r25, X+
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ld r24, X+
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sts 0x5E,r24 /*sph*/
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sts 0x5D ,r25 /*spl*/
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/*restore registers from stack*/
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pop r29
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pop r28
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pop r17
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pop r16
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pop r15
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pop r14
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pop r13
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pop r12
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pop r11
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pop r10
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pop r9
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pop r8
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pop r7
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pop r6
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pop r5
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pop r4
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pop r3
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pop r2
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/*restore sreg*/
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ld r25, X
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sts 0x5f,r25 /*sreg*/
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pop r30
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pop r31
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IJMP
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ret
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/*PAGE
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*
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* _CPU_Context_Initialize
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*
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* This kernel routine initializes the basic non-FP context area associated
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* with each thread.
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*
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* Input parameters:
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* the_context - pointer to the context area
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* stack_base - address of memory for the SPARC
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* size - size in bytes of the stack area
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* new_level - interrupt level for this context area
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* entry_point - the starting execution point for this this context
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* is_fp - TRUE if this context is associated with an FP thread
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*
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* the_context is in r25,r24
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* entry point is in r13,r12
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* stack base is in r23, r22
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* size is in r21, r20, r19,r18
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* newleve is in r14,r15, r16, 17
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*
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*
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* Output parameters: NONE
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*/
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PUBLIC(_CPU_Context_Initialize)
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SYM(_CPU_Context_Initialize):
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//save caller saved regs
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PUSH R10
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PUSH R11
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PUSH R12
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PUSH R13
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PUSH R14
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PUSH R15
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PUSH R16
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PUSH R17
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PUSH R28
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PUSH R29
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//calculate new stack pointer
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ADD R22, R18
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ADC R23, R19
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MOV R26, R22
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MOV R27, R23
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//Initialize stack with entry point
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ST -X, R13
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ST -X, R12
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//store new stack pointer in context control
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SBIW R26, 0X13 /*subtract 33 to account for registers*/
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MOV R28, R24
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MOV R29, R25
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STD Y+1, R27 //save stack pointer high to context control
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ST Y, R26 //save stack pointer low to context control
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//set interrupt level in new context
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LDI R18, 0 //set sreg in new context to zero
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STD Y+2, R18 //interrupts not enabled
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MOV R18, R14
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CPI R18, 0
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BRNE NEW_LEVEL_ZERO
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LDI R18, 0X80 //set sreg in new context to 0x80
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STD Y+2, R18 //interupts enabled
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NEW_LEVEL_ZERO:
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//restore caller saved regs
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POP R29
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POP R28
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POP R17
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POP R16
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POP R15
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POP R14
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POP R13
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POP R12
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POP R11
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POP R10
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RET
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/* void __ISR_Handler()
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*
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* This routine provides the RTEMS interrupt management.
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*
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* NO_CPU Specific Information:
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*
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* XXX document implementation including references if appropriate
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void _ISR_Handler(void)
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{
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*/
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/*
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* This discussion ignores a lot of the ugly details in a real
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* implementation such as saving enough registers/state to be
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* able to do something real. Keep in mind that the goal is
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* to invoke a user's ISR handler which is written in C and
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* uses a certain set of registers.
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*
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* Also note that the exact order is to a large extent flexible.
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* Hardware will dictate a sequence for a certain subset of
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* _ISR_Handler while requirements for setting
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*/
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/*
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* At entry to "common" _ISR_Handler, the vector number must be
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* available. On some CPUs the hardware puts either the vector
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* number or the offset into the vector table for this ISR in a
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* known place. If the hardware does not give us this information,
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* then the assembly portion of RTEMS for this port will contain
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* a set of distinct interrupt entry points which somehow place
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* the vector number in a known place (which is safe if another
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* interrupt nests this one) and branches to _ISR_Handler.
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*
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* save some or all context on stack
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* may need to save some special interrupt information for exit
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*
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* #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
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* if ( _ISR_Nest_level == 0 )
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* switch to software interrupt stack
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* #endif
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*
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* _ISR_Nest_level++;
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*
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* _Thread_Dispatch_disable_level++;
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*
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* (*_ISR_Vector_table[ vector ])( vector );
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*
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* _Thread_Dispatch_disable_level--;
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*
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* --_ISR_Nest_level;
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*
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* if ( _ISR_Nest_level )
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* goto the label "exit interrupt (simple case)"
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*
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* if ( _Thread_Dispatch_disable_level )
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* goto the label "exit interrupt (simple case)"
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*
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* if ( _Thread_Dispatch_necessary ) {
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* call _Thread_Dispatch() or prepare to return to _ISR_Dispatch
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* prepare to get out of interrupt
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* return from interrupt (maybe to _ISR_Dispatch)
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*
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* LABEL "exit interrupt (simple case):
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* #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
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* if outermost interrupt
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* restore stack
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* #endif
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* prepare to get out of interrupt
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* return from interrupt
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*/
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/*} */
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PUBLIC(_ISR_Handler)
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SYM(_ISR_Handler):
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ret
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