forked from Imagelibrary/rtems
9964895866
Adjust build support files to new directory layout. This patch is a part of the BSP source reorganization. Update #3285.
77 lines
2.2 KiB
C
77 lines
2.2 KiB
C
/*
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* Copyright (c) 2013-2014 embedded brains GmbH. All rights reserved.
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*
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* embedded brains GmbH
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* Dornierstr. 4
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* 82178 Puchheim
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* Germany
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* <info@embedded-brains.de>
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#define ARM_CP15_TEXT_SECTION BSP_START_TEXT_SECTION
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#include <bsp.h>
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#include <bsp/start.h>
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#include <bsp/arm-cp15-start.h>
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#include <bsp/arm-a9mpcore-start.h>
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BSP_START_TEXT_SECTION void bsp_start_hook_0(void)
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{
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uint32_t sctlr_val;
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sctlr_val = arm_cp15_get_control();
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/*
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* Current U-boot loader seems to start kernel image
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* with I and D caches on and MMU enabled.
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* If RTEMS application image finds that cache is on
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* during startup then disable caches.
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*/
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if ( sctlr_val & (ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M ) ) {
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if ( sctlr_val & (ARM_CP15_CTRL_C | ARM_CP15_CTRL_M ) ) {
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/*
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* If the data cache is on then ensure that it is clean
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* before switching off to be extra carefull.
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*/
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arm_cp15_data_cache_clean_all_levels();
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}
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arm_cp15_flush_prefetch_buffer();
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sctlr_val &= ~ ( ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M | ARM_CP15_CTRL_A );
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arm_cp15_set_control( sctlr_val );
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}
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arm_cp15_instruction_cache_invalidate();
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/*
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* The care should be taken there that no shared levels
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* are invalidated by secondary CPUs in SMP case.
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* It is not problem on Zynq because level of coherency
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* is L1 only and higher level is not maintained and seen
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* by CP15. So no special care to limit levels on the secondary
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* are required there.
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*/
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arm_cp15_data_cache_invalidate_all_levels();
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arm_cp15_branch_predictor_invalidate_all();
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arm_cp15_tlb_invalidate();
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arm_cp15_flush_prefetch_buffer();
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arm_a9mpcore_start_hook_0();
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}
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BSP_START_TEXT_SECTION void bsp_start_hook_1(void)
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{
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arm_a9mpcore_start_hook_1();
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bsp_start_copy_sections();
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zynq_setup_mmu_and_cache();
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#if !defined(RTEMS_SMP) \
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&& (defined(BSP_DATA_CACHE_ENABLED) \
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|| defined(BSP_INSTRUCTION_CACHE_ENABLED))
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/* Enable unified L2 cache */
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rtems_cache_enable_data();
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#endif
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bsp_start_clear_bss();
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}
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