forked from Imagelibrary/rtems
511dc4b2be
Statically initialize the interrupt stack area
(_Configuration_Interrupt_stack_area_begin,
_Configuration_Interrupt_stack_area_end, and
_Configuration_Interrupt_stack_size) via <rtems/confdefs.h>. Place the
interrupt stack area in a special section ".rtemsstack.interrupt". Let
BSPs define the optimal placement of this section in their linker
command files (e.g. in a fast on-chip memory).
This change makes makes the CPU_HAS_SOFTWARE_INTERRUPT_STACK and
CPU_HAS_HARDWARE_INTERRUPT_STACK CPU port defines superfluous, since the
low level initialization code has all information available via global
symbols.
This change makes the CPU_ALLOCATE_INTERRUPT_STACK CPU port define
superfluous, since the interrupt stacks are allocated by confdefs.h for
all architectures. There is no need for BSP-specific linker command
file magic (except the section placement), see previous ARM linker
command file as a bad example.
Remove _CPU_Install_interrupt_stack(). Initialize the hardware
interrupt stack in _CPU_Initialize() if necessary (e.g.
m68k_install_interrupt_stack()).
The optional _CPU_Interrupt_stack_setup() is still useful to customize
the registration of the interrupt stack area in the per-CPU information.
The initialization stack can reuse the interrupt stack, since
* interrupts are disabled during the sequential system initialization,
and
* the boot_card() function does not return.
This stack resuse saves memory.
Changes per architecture:
arm:
* Mostly replace the linker symbol based configuration of stacks with
the standard <rtems/confdefs.h> configuration via
CONFIGURE_INTERRUPT_STACK_SIZE. The size of the FIQ, ABT and UND
mode stack is still defined via linker symbols. These modes are
rarely used in applications and the default values provided by the
BSP should be sufficient in most cases.
* Remove the bsp_processor_count linker symbol hack used for the SMP
support. This is possible since the interrupt stack area is now
allocated by the linker and not allocated from the heap. This makes
some configure.ac stuff obsolete. Remove the now superfluous BSP
variants altcycv_devkit_smp and realview_pbx_a9_qemu_smp.
bfin:
* Remove unused magic linker command file allocation of initialization
stack. Maybe a previous linker command file copy and paste problem?
In the start.S the initialization stack is set to a hard coded value.
lm32, m32c, mips, nios2, riscv, sh, v850:
* Remove magic linker command file allocation of initialization stack.
Reuse interrupt stack for initialization stack.
m68k:
* Remove magic linker command file allocation of initialization stack.
Reuse interrupt stack for initialization stack.
powerpc:
* Remove magic linker command file allocation of initialization stack.
Reuse interrupt stack for initialization stack.
* Used dedicated memory region (REGION_RTEMSSTACK) for the interrupt
stack on BSPs using the shared linkcmds.base (replacement for
REGION_RWEXTRA).
sparc:
* Remove the hard coded initialization stack. Use the interrupt stack
for the initialization stack on the boot processor. This saves
16KiB of RAM.
Update #3459.
# Goal is to have BSPs build almost completely automatically from a template # and information that comes from SOPC Builder as a .PTF file. Most of the # code will go to a shared/ BSP directory. # # Ideally, updates to the PTF shouldn't cause any pain for the maintainer # of a specific BSP (possibly with enhancements not covered by the # automatic BSP creation). # # Some first steps toward utilizing SOPC Builder PTF output can be found # in top level /tools/cpu/nios2. Also see the README there. # # Implemented (in shared/ subdirectory) # Clock driver # Timer driver # Console via JTAG UART # # Todo; # Support more peripherals. My priorities: # - (improve) Altera Avalon JTAG UART # - Altera Avalon UART # - OpenCores.org I2C Master # - Altera SPI Core / EPCS Configuration Device # - OpenCores.org 10/100 Ethernet MAC (use existing driver) # - (more) Altera Avalon Timer # # Put all drivers aside in a shared/ subdirectory. # Update the "times" file for NIOS2 with and without icache. # # Missing (although it looks like it's there) # Data cache handling (for now, don't use the "fast" NIOS2) # SHM support (just taken over the code from no_cpu/no_bsp) # # Kolja Waschk, 6/2006 # BSP NAME: nios2_eb2_1 BOARD: Altera Instruction Set Simulator Default plus second timer BUS: Avalon CPU FAMILY: nios2 CPU: small COPROCESSORS: none MODE: 32 bit mode DEBUG MONITOR: none PERIPHERALS =========== TIMERS: Altera Avalon Timer RESOLUTION: .0001 microseconds SERIAL PORTS: Altera Avalon JTAG UART REAL-TIME CLOCK: none DMA: none VIDEO: none SCSI: none NETWORKING: none DRIVER INFORMATION ================== CLOCK DRIVER: Altera Avalon Timer IOSUPP DRIVER: none SHMSUPP: polled TIMER DRIVER: Altera Avalon Timer TTY DRIVER: none STDIO ===== PORT: Console port 0 ELECTRICAL: JTAG BAUD: 115200 BITS PER CHARACTER: 8 PARITY: None STOP BITS: 1 NOTES =====