forked from Imagelibrary/rtems
be6e30dff3
The RTEMS Software Engineering Guide specifies that the SPDX license annotation shouldbe the first line of the file and not part of the copyright/license comment block.
127 lines
3.6 KiB
C
127 lines
3.6 KiB
C
/* SPDX-License-Identifier: BSD-2-Clause */
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/**
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* @file
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* @ingroup zynq_interrupt
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* @brief Interrupt definitions.
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*/
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/*
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* Copyright (C) 2013 embedded brains GmbH & Co. KG
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef LIBBSP_ARM_XILINX_ZYNQ_IRQ_H
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#define LIBBSP_ARM_XILINX_ZYNQ_IRQ_H
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#ifndef ASM
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#include <rtems/irq-extension.h>
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#include <bsp/arm-a9mpcore-irq.h>
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#include <dev/irq/arm-gic-irq.h>
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#ifdef __cplusplus
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extern "C" {
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#endif /* __cplusplus */
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/**
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* @defgroup zynq_interrupt Interrupt Support
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* @ingroup RTEMSBSPsARMZynq
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* @brief Interrupt Support
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* @{
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*/
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#define ZYNQ_IRQ_CPU_0 32
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#define ZYNQ_IRQ_CPU_1 33
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#define ZYNQ_IRQ_L2_CACHE 34
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#define ZYNQ_IRQ_OCM 35
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#define ZYNQ_IRQ_PMU_0 37
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#define ZYNQ_IRQ_PMU_1 38
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#define ZYNQ_IRQ_XADC 39
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#define ZYNQ_IRQ_DVI 40
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#define ZYNQ_IRQ_SWDT 41
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#define ZYNQ_IRQ_TTC_0_0 42
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#define ZYNQ_IRQ_TTC_1_0 43
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#define ZYNQ_IRQ_TTC_2_0 44
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#define ZYNQ_IRQ_DMAC_ABORT 45
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#define ZYNQ_IRQ_DMAC_0 46
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#define ZYNQ_IRQ_DMAC_1 47
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#define ZYNQ_IRQ_DMAC_2 48
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#define ZYNQ_IRQ_DMAC_3 49
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#define ZYNQ_IRQ_SMC 50
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#define ZYNQ_IRQ_QUAD_SPI 51
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#define ZYNQ_IRQ_GPIO 52
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#define ZYNQ_IRQ_USB_0 53
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#define ZYNQ_IRQ_ETHERNET_0 54
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#define ZYNQ_IRQ_ETHERNET_0_WAKEUP 55
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#define ZYNQ_IRQ_SDIO_0 56
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#define ZYNQ_IRQ_I2C_0 57
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#define ZYNQ_IRQ_SPI_0 58
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#define ZYNQ_IRQ_UART_0 59
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#define ZYNQ_IRQ_CAN_0 60
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#define ZYNQ_IRQ_FPGA_0 61
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#define ZYNQ_IRQ_FPGA_1 62
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#define ZYNQ_IRQ_FPGA_2 63
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#define ZYNQ_IRQ_FPGA_3 64
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#define ZYNQ_IRQ_FPGA_4 65
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#define ZYNQ_IRQ_FPGA_5 66
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#define ZYNQ_IRQ_FPGA_6 67
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#define ZYNQ_IRQ_FPGA_7 68
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#define ZYNQ_IRQ_TTC_0_1 69
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#define ZYNQ_IRQ_TTC_1_1 70
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#define ZYNQ_IRQ_TTC_2_1 71
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#define ZYNQ_IRQ_DMAC_4 72
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#define ZYNQ_IRQ_DMAC_5 73
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#define ZYNQ_IRQ_DMAC_6 74
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#define ZYNQ_IRQ_DMAC_7 75
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#define ZYNQ_IRQ_USB_1 76
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#define ZYNQ_IRQ_ETHERNET_1 77
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#define ZYNQ_IRQ_ETHERNET_1_WAKEUP 78
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#define ZYNQ_IRQ_SDIO_1 79
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#define ZYNQ_IRQ_I2C_1 80
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#define ZYNQ_IRQ_SPI_1 81
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#define ZYNQ_IRQ_UART_1 82
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#define ZYNQ_IRQ_CAN_1 83
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#define ZYNQ_IRQ_FPGA_8 84
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#define ZYNQ_IRQ_FPGA_9 85
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#define ZYNQ_IRQ_FPGA_10 86
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#define ZYNQ_IRQ_FPGA_11 87
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#define ZYNQ_IRQ_FPGA_12 88
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#define ZYNQ_IRQ_FPGA_13 89
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#define ZYNQ_IRQ_FPGA_14 90
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#define ZYNQ_IRQ_FPGA_15 91
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#define ZYNQ_IRQ_PARITY 92
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#define BSP_INTERRUPT_VECTOR_COUNT 93
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/** @} */
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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#endif /* ASM */
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#endif /* LIBBSP_ARM_XILINX_ZYNQ_IRQ_H */
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