forked from Imagelibrary/rtems
d735d4459c
This BSP supports a custom STM32U5 based board. It uses a similar structure like the existing STM32H7 BSP and therefore should be well adaptable to other boards. Co-authored-by: Christian Mauderer <christian.mauderer@embedded-brains.de>
222 lines
7.7 KiB
C
222 lines
7.7 KiB
C
/* SPDX-License-Identifier: BSD-2-Clause */
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/**
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* @file
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*
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* @ingroup RTEMSBSPsARMSTM32U5
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*
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* @brief Implementation of OctoSPI initialization
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*/
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/*
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* Copyright (C) 2024 embedded brains GmbH & Co. KG
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <bsp.h>
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#include <bsp/fatal.h>
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#include <bsp/start.h>
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#include <stm32u5/hal.h>
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void BSP_START_TEXT_SECTION stm32u5_init_octospi( void )
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{
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OSPI_HandleTypeDef hospi1 = {
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.Instance = OCTOSPI1,
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.Init = {
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.FifoThreshold = 2,
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.DualQuad = HAL_OSPI_DUALQUAD_DISABLE,
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.MemoryType = HAL_OSPI_MEMTYPE_HYPERBUS,
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.DeviceSize = 24,
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.ChipSelectHighTime = 1, /* min 6ns -> 1 works for up to 160MHz */
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.FreeRunningClock = HAL_OSPI_FREERUNCLK_DISABLE,
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.ClockMode = HAL_OSPI_CLOCK_MODE_0,
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/*
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* FIXME: Enable Hybrid burst in CR0 of the RAM and set to a sensible
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* WrapSize
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*/
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.WrapSize = HAL_OSPI_WRAP_NOT_SUPPORTED,
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.ClockPrescaler = 2,
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/*
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* Reference Manual: The firmware must clear SSHIFT when the data phase is
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* configured in DTR mode (DDTR = 1).
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*/
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.SampleShifting = HAL_OSPI_SAMPLE_SHIFTING_NONE,
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/*
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* Reference Manual: In DTR mode, it is recommended to set DHQC of
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* OCTOSPI_TCR, to shift the outputs by a quarter of cycle and avoid
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* holding issues on the memory side.
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*/
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.DelayHoldQuarterCycle = HAL_OSPI_DHQC_ENABLE,
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.ChipSelectBoundary = 7,
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.DelayBlockBypass = HAL_OSPI_DELAY_BLOCK_USED,
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.MaxTran = 0,
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.Refresh = 241, /* based on AN5050 */
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},
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};
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OSPIM_CfgTypeDef sOspiManagerCfg = {
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.ClkPort = 1,
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.DQSPort = 1,
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.NCSPort = 1,
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.IOLowPort = HAL_OSPIM_IOPORT_1_LOW,
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.IOHighPort = HAL_OSPIM_IOPORT_1_HIGH,
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};
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OSPI_HyperbusCfgTypeDef sHyperBusCfg = {
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/*
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* S70KL1282 in 166MHz version needs at least 36ns. At 100MHz that's 3.6
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* clock cycles.
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*/
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.RWRecoveryTime = 4,
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/*
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* FIXME: That's the Clock latency. We could set the RAM config register to
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* 4 clock latencies for 100 MHz.
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*/
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.AccessTime = 7,
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.WriteZeroLatency = HAL_OSPI_LATENCY_ON_WRITE,
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/* 128-Mb version of S70KL1282 only supports fixed latency */
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.LatencyMode = HAL_OSPI_FIXED_LATENCY,
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};
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OSPI_HyperbusCmdTypeDef sCommand = {
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.AddressSpace = HAL_OSPI_MEMORY_ADDRESS_SPACE,
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.AddressSize = HAL_OSPI_ADDRESS_32_BITS,
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.DQSMode = HAL_OSPI_DQS_ENABLE,
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.Address = 0,
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.NbData = 1,
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};
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OSPI_MemoryMappedTypeDef sMemMappedCfg = {
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.TimeOutActivation = HAL_OSPI_TIMEOUT_COUNTER_ENABLE,
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.TimeOutPeriod = 0x20,
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};
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HAL_OSPI_DLYB_CfgTypeDef HAL_OSPI_DLYB_Cfg_Struct = { 0 };
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if ( HAL_OSPIM_Config(
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&hospi1,
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&sOspiManagerCfg,
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HAL_OSPI_TIMEOUT_DEFAULT_VALUE
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) != HAL_OK ) {
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bsp_fatal( STM32U5_FATAL_OSPI );
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}
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if ( HAL_OSPI_Init( &hospi1 ) != HAL_OK ) {
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bsp_fatal( STM32U5_FATAL_OSPI );
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}
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if ( HAL_OSPI_HyperbusCfg(
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&hospi1,
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&sHyperBusCfg,
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HAL_OSPI_TIMEOUT_DEFAULT_VALUE
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) != HAL_OK ) {
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bsp_fatal( STM32U5_FATAL_OSPI );
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}
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/* Delay block tuning */
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if ( HAL_OSPI_DLYB_GetClockPeriod( &hospi1, &HAL_OSPI_DLYB_Cfg_Struct ) !=
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HAL_OK ) {
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bsp_fatal( STM32U5_FATAL_OSPI );
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}
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/* From ST example: Set at one quarter. */
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HAL_OSPI_DLYB_Cfg_Struct.PhaseSel /= 4;
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if ( HAL_OSPI_DLYB_SetConfig( &hospi1, &HAL_OSPI_DLYB_Cfg_Struct ) !=
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HAL_OK ) {
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bsp_fatal( STM32U5_FATAL_OSPI );
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}
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/* Memory-mapped mode configuration */
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if ( HAL_OSPI_HyperbusCmd(
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&hospi1,
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&sCommand,
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HAL_OSPI_TIMEOUT_DEFAULT_VALUE
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) != HAL_OK ) {
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bsp_fatal( STM32U5_FATAL_OSPI );
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}
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/* OctoSPI activation of memory-mapped mode */
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if ( HAL_OSPI_MemoryMapped( &hospi1, &sMemMappedCfg ) != HAL_OK ) {
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bsp_fatal( STM32U5_FATAL_OSPI );
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}
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}
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void BSP_START_TEXT_SECTION HAL_OSPI_MspInit( OSPI_HandleTypeDef *hospi )
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{
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GPIO_InitTypeDef GPIO_InitStruct = { 0 };
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RCC_PeriphCLKInitTypeDef PeriphClkInit = { 0 };
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if ( hospi->Instance == OCTOSPI1 ) {
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/* Initializes the peripherals clock */
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PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_OSPI;
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PeriphClkInit.OspiClockSelection = RCC_OSPICLKSOURCE_PLL2;
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PeriphClkInit.PLL2.PLL2Source = RCC_PLLSOURCE_MSI;
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PeriphClkInit.PLL2.PLL2M = 3;
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PeriphClkInit.PLL2.PLL2N = 12;
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PeriphClkInit.PLL2.PLL2P = 2;
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PeriphClkInit.PLL2.PLL2Q = 1;
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PeriphClkInit.PLL2.PLL2R = 2;
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PeriphClkInit.PLL2.PLL2RGE = RCC_PLLVCIRANGE_1;
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PeriphClkInit.PLL2.PLL2FRACN = 4096.0;
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PeriphClkInit.PLL2.PLL2ClockOut = RCC_PLL2_DIVQ;
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if ( HAL_RCCEx_PeriphCLKConfig( &PeriphClkInit ) != HAL_OK ) {
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bsp_fatal( STM32U5_FATAL_OSPI );
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}
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/* Peripheral clock enable */
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__HAL_RCC_OSPIM_CLK_ENABLE();
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__HAL_RCC_OSPI1_CLK_ENABLE();
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__HAL_RCC_GPIOE_CLK_ENABLE();
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__HAL_RCC_GPIOC_CLK_ENABLE();
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/* OCTOSPI1 GPIO Configuration */
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GPIO_InitStruct.Pin = GPIO_PIN_3;
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GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
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GPIO_InitStruct.Pull = GPIO_NOPULL;
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GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
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GPIO_InitStruct.Alternate = GPIO_AF3_OCTOSPI1;
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HAL_GPIO_Init( GPIOE, &GPIO_InitStruct );
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GPIO_InitStruct.Pin = GPIO_PIN_0;
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GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
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GPIO_InitStruct.Pull = GPIO_NOPULL;
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GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
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GPIO_InitStruct.Alternate = GPIO_AF3_OCTOSPI1;
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HAL_GPIO_Init( GPIOC, &GPIO_InitStruct );
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GPIO_InitStruct.Pin = GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3;
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GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
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GPIO_InitStruct.Pull = GPIO_NOPULL;
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GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
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GPIO_InitStruct.Alternate = GPIO_AF10_OCTOSPI1;
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HAL_GPIO_Init( GPIOC, &GPIO_InitStruct );
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GPIO_InitStruct.Pin = GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 |
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GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15;
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GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
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GPIO_InitStruct.Pull = GPIO_NOPULL;
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GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
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GPIO_InitStruct.Alternate = GPIO_AF10_OCTOSPI1;
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HAL_GPIO_Init( GPIOE, &GPIO_InitStruct );
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}
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}
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