forked from Imagelibrary/rtems
155 lines
3.7 KiB
C
155 lines
3.7 KiB
C
/* SPDX-License-Identifier: BSD-2-Clause */
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/*
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* Copyright (c) 2016 embedded brains GmbH & Co. KG
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <rtems.h>
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#include <chip.h>
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#define CPU_DATA_CACHE_ALIGNMENT 32
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#define CPU_INSTRUCTION_CACHE_ALIGNMENT 32
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#define CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS
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static inline void _CPU_cache_flush_data_range(
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const void *d_addr,
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size_t n_bytes
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)
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{
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SCB_CleanInvalidateDCache_by_Addr(
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RTEMS_DECONST(uint32_t *, (const uint32_t *) d_addr),
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n_bytes
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);
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}
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static inline void _CPU_cache_invalidate_data_range(
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const void *d_addr,
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size_t n_bytes
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)
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{
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SCB_InvalidateDCache_by_Addr(
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RTEMS_DECONST(uint32_t *, (const uint32_t *) d_addr),
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n_bytes
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);
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}
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static inline void _CPU_cache_freeze_data(void)
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{
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/* TODO */
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}
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static inline void _CPU_cache_unfreeze_data(void)
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{
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/* TODO */
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}
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static inline void _CPU_cache_invalidate_instruction_range(
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const void *i_addr,
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size_t n_bytes
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)
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{
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rtems_interrupt_level level;
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rtems_interrupt_disable(level);
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SCB_InvalidateICache();
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rtems_interrupt_enable(level);
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}
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static inline void _CPU_cache_freeze_instruction(void)
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{
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/* TODO */
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}
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static inline void _CPU_cache_unfreeze_instruction(void)
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{
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/* TODO */
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}
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static inline void _CPU_cache_flush_entire_data(void)
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{
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rtems_interrupt_level level;
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rtems_interrupt_disable(level);
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SCB_CleanDCache();
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rtems_interrupt_enable(level);
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}
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static inline void _CPU_cache_invalidate_entire_data(void)
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{
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rtems_interrupt_level level;
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rtems_interrupt_disable(level);
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SCB_InvalidateDCache();
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rtems_interrupt_enable(level);
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}
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static inline void _CPU_cache_enable_data(void)
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{
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rtems_interrupt_level level;
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rtems_interrupt_disable(level);
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SCB_EnableDCache();
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rtems_interrupt_enable(level);
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}
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static inline void _CPU_cache_disable_data(void)
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{
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rtems_interrupt_level level;
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rtems_interrupt_disable(level);
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SCB_DisableDCache();
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rtems_interrupt_enable(level);
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}
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static inline void _CPU_cache_invalidate_entire_instruction(void)
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{
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rtems_interrupt_level level;
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rtems_interrupt_disable(level);
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SCB_InvalidateICache();
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rtems_interrupt_enable(level);
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}
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static inline void _CPU_cache_enable_instruction(void)
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{
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rtems_interrupt_level level;
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rtems_interrupt_disable(level);
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SCB_EnableICache();
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rtems_interrupt_enable(level);
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}
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static inline void _CPU_cache_disable_instruction(void)
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{
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rtems_interrupt_level level;
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rtems_interrupt_disable(level);
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SCB_DisableICache();
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rtems_interrupt_enable(level);
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}
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#include "../../shared/cache/cacheimpl.h"
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