forked from Imagelibrary/rtems
be6e30dff3
The RTEMS Software Engineering Guide specifies that the SPDX license annotation shouldbe the first line of the file and not part of the copyright/license comment block.
418 lines
13 KiB
C
418 lines
13 KiB
C
/* SPDX-License-Identifier: BSD-2-Clause */
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/**
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* @file
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*
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* @ingroup arm_beagle
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*
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* @brief Support for PWM for the BeagleBone Black.
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*/
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/*
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* Copyright (c) 2016 Punit Vara <punitvara@gmail.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/** This file is based on
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* https://github.com/VegetableAvenger/BBBIOlib/blob/master/BBBio_lib/BBBiolib_PWMSS.c
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*/
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#include <libcpu/am335x.h>
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#include <stdio.h>
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#include <bsp/gpio.h>
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#include <bsp/bbb-gpio.h>
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#include <bsp.h>
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#include <bsp/pwmss.h>
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#include <bsp/bbb-pwm.h>
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#include <bsp/beagleboneblack.h>
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/* Currently these definitions are for BeagleBone Black board only
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* Later on Beagle-xM board support can be added in this code.
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* After support gets added if condition should be removed
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*/
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#if IS_AM335X
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/*
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* @brief This function selects EPWM module to be enabled
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*
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* @param pwm_id It is the instance number of EPWM of pwm sub system.
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*
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* @return Base Address of respective pwm instant.
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*/
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static uint32_t select_pwm(BBB_PWMSS pwm_id)
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{
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uint32_t baseAddr=0;
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if (pwm_id == BBB_PWMSS0) {
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baseAddr = AM335X_EPWM_0_REGS;
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} else if (pwm_id == BBB_PWMSS1) {
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baseAddr = AM335X_EPWM_1_REGS;
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} else if (pwm_id == BBB_PWMSS2) {
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baseAddr = AM335X_EPWM_2_REGS;
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} else {
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baseAddr = 0;
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}
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return baseAddr;
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}
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/*
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* @brief This function selects PWM Sub system to be enabled
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*
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* @param pwmss_id The instance number of ePWMSS whose system clocks
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* have to be configured.
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*
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* @return Base Address of respective pwmss instant.
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*/
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static uint32_t select_pwmss(BBB_PWMSS pwmss_id)
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{
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uint32_t baseAddr=0;
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if (pwmss_id == BBB_PWMSS0) {
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baseAddr = AM335X_PWMSS0_MMAP_ADDR;
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} else if (pwmss_id == BBB_PWMSS1) {
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baseAddr = AM335X_PWMSS1_MMAP_ADDR;
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} else if (pwmss_id == BBB_PWMSS2) {
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baseAddr = AM335X_PWMSS2_MMAP_ADDR;
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} else {
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baseAddr = 0;
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}
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return baseAddr;
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}
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bool beagle_pwm_pinmux_setup(bbb_pwm_pin_t pin_no, BBB_PWMSS pwm_id)
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{
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bool is_valid = true;
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if(pwm_id == BBB_PWMSS0) {
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if (pin_no == BBB_P9_21_0B) {
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REG(AM335X_PADCONF_BASE + AM335X_CONF_SPI0_D0) = BBB_MUXMODE(BBB_P9_21_MUX_PWM);
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} else if (pin_no == BBB_P9_22_0A) {
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REG(AM335X_PADCONF_BASE + AM335X_CONF_SPI0_SCLK) = BBB_MUXMODE(BBB_P9_22_MUX_PWM);
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} else if (pin_no == BBB_P9_29_0B) {
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REG(AM335X_PADCONF_BASE + AM335X_CONF_MCASP0_FSX) = BBB_MUXMODE(BBB_P9_29_MUX_PWM);
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} else if (pin_no == BBB_P9_31_0A) {
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REG(AM335X_PADCONF_BASE + AM335X_CONF_MCASP0_ACLKX) = BBB_MUXMODE(BBB_P9_31_MUX_PWM);
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} else {
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is_valid = false;
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}
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} else if (pwm_id == BBB_PWMSS1) {
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if (pin_no == BBB_P8_34_1B) {
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REG(AM335X_PADCONF_BASE + BBB_CONTROL_CONF_LCD_DATA(11)) = BBB_MUXMODE(BBB_P8_34_MUX_PWM);
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} else if (pin_no == BBB_P8_36_1A) {
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REG(AM335X_PADCONF_BASE + BBB_CONTROL_CONF_LCD_DATA(10)) = BBB_MUXMODE(BBB_P8_36_MUX_PWM);
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} else if (pin_no == BBB_P9_14_1A) {
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REG(AM335X_PADCONF_BASE + AM335X_CONF_GPMC_A2) = BBB_MUXMODE(BBB_P9_14_MUX_PWM);
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} else if (pin_no == BBB_P9_16_1B) {
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REG(AM335X_PADCONF_BASE + AM335X_CONF_GPMC_A3) = BBB_MUXMODE(BBB_P9_16_MUX_PWM);
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} else {
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is_valid = false;
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}
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} else if (pwm_id == BBB_PWMSS2) {
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if (pin_no == BBB_P8_13_2B) {
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REG(AM335X_PADCONF_BASE + BBB_CONTROL_CONF_GPMC_AD(9)) = BBB_MUXMODE(BBB_P8_13_MUX_PWM);
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} else if (pin_no == BBB_P8_19_2A) {
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REG(AM335X_PADCONF_BASE + BBB_CONTROL_CONF_GPMC_AD(8)) = BBB_MUXMODE(BBB_P8_19_MUX_PWM);
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} else if (pin_no == BBB_P8_45_2A) {
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REG(AM335X_PADCONF_BASE + BBB_CONTROL_CONF_LCD_DATA(0)) = BBB_MUXMODE(BBB_P8_45_MUX_PWM);
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} else if (pin_no == BBB_P8_46_2B) {
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REG(AM335X_PADCONF_BASE + BBB_CONTROL_CONF_LCD_DATA(1)) = BBB_MUXMODE(BBB_P8_46_MUX_PWM);
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} else {
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is_valid = false;
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}
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} else {
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is_valid = false;
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}
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return is_valid;
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}
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/**
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* @brief This function Enables TBCLK(Time Base Clock) for specific
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* EPWM instance of pwmsubsystem.
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*
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* @param instance It is the instance number of EPWM of pwmsubsystem.
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*
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* @return true if successful
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* false if unsuccessful
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**/
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static bool pwmss_tbclk_enable(BBB_PWMSS instance)
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{
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uint32_t enable_bit;
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bool is_valid = true;
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if (instance == BBB_PWMSS0) {
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enable_bit = AM335X_PWMSS_CTRL_PWMSS0_TBCLKEN;
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} else if (instance == BBB_PWMSS1) {
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enable_bit = AM335X_PWMSS_CTRL_PWMSS1_TBCLKEN;
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} else if (instance == BBB_PWMSS2) {
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enable_bit = AM335X_PWMSS_CTRL_PWMSS2_TBCLKEN;
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} else {
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is_valid = false;
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}
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if (is_valid)
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{
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REG(AM335X_PADCONF_BASE + AM335X_PWMSS_CTRL) |= enable_bit;
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}
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return is_valid;
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}
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/**
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* @brief This functions enables clock for EHRPWM module in PWMSS subsystem.
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*
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* @param pwm_id It is the instance number of EPWM of pwm sub system.
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*
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* @return true if successful
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* false if unsuccessful
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*
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**/
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static bool pwm_clock_enable(BBB_PWMSS pwm_id)
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{
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const bool id_is_valid = pwm_id < BBB_PWMSS_COUNT;
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bool status = true;
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if (id_is_valid) {
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const uint32_t baseAddr = select_pwmss(pwm_id);
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REG(baseAddr + AM335X_PWMSS_CLKCONFIG) |= AM335X_PWMSS_CLK_EN_ACK;
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} else {
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status = false;
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}
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return status;
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}
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bool beagle_pwm_init(BBB_PWMSS pwmss_id)
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{
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const bool id_is_valid = pwmss_id < BBB_PWMSS_COUNT;
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bool status = true;
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if(id_is_valid) {
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pwmss_module_clk_config(pwmss_id);
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pwm_clock_enable(pwmss_id);
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pwmss_tbclk_enable(pwmss_id);
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} else {
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status =false;
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}
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return status;
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}
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int beagle_pwm_configure(BBB_PWMSS pwm_id, float pwm_freq, float duty_a, float duty_b)
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{
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uint32_t baseAddr;
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int status = 1;
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float cycle = 0.0f,divisor = 0;
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unsigned int i,j;
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const float CLKDIV_div[] = {1.0,2.0,4.0,8.0,16.0,32.0,64.0,128.0};
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const float HSPCLKDIV_div[] = {1.0, 2.0, 4.0, 6.0, 8.0, 10.0,12.0, 14.0};
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int NearCLKDIV =7,NearHSPCLKDIV =7,NearTBPRD =0;
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if (pwm_freq <= BBB_PWM_FREQ_THRESHOLD) {
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status =0;
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}
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if (duty_a < 0.0f || duty_a > 100.0f || duty_b < 0.0f || duty_b > 100.0f) {
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status = 0;
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}
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duty_a /= 100.0f;
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duty_b /= 100.0f;
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/** 10^9 /Hz compute time per cycle (ns) */
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cycle = 1000000000.0f / pwm_freq;
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/** am335x provide (128* 14) divider and per TBPRD means 10ns when divider
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* and max TBPRD is 65535 so max cycle is 128 * 8 * 14 * 65535 * 10ns */
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divisor = (cycle / 655350.0f);
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if (divisor > (128 * 14)) {
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return 0;
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}
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else {
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for (i=0;i<8;i++) {
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for(j=0 ; j<8; j++) {
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if((CLKDIV_div[i] * HSPCLKDIV_div[j]) < (CLKDIV_div[NearCLKDIV]
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* HSPCLKDIV_div[NearHSPCLKDIV]) && (CLKDIV_div[i] * HSPCLKDIV_div[j] > divisor)) {
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NearCLKDIV = i;
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NearHSPCLKDIV = j;
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}
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}
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}
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baseAddr = select_pwm(pwm_id);
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REG16(baseAddr + AM335X_EPWM_TBCTL) &= ~(AM335X_TBCTL_CLKDIV_MASK | AM335X_TBCTL_HSPCLKDIV_MASK);
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const uint16_t clkdiv_clear = (REG16(baseAddr + AM335X_EPWM_TBCTL) &
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(~AM335X_EPWM_TBCTL_CLKDIV));
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const uint16_t clkdiv_write = ((NearCLKDIV
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<< AM335X_EPWM_TBCTL_CLKDIV_SHIFT) & AM335X_EPWM_TBCTL_CLKDIV);
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REG16(baseAddr + AM335X_EPWM_TBCTL) = clkdiv_clear | clkdiv_write;
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const uint16_t hspclkdiv_clear = (REG16(baseAddr + AM335X_EPWM_TBCTL) &
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(~AM335X_EPWM_TBCTL_HSPCLKDIV));
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const uint16_t hspclkdiv_write = ((NearHSPCLKDIV <<
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AM335X_EPWM_TBCTL_HSPCLKDIV_SHIFT) & AM335X_EPWM_TBCTL_HSPCLKDIV);
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REG16(baseAddr + AM335X_EPWM_TBCTL) = hspclkdiv_clear | hspclkdiv_write;
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NearTBPRD = (cycle / (10.0 * CLKDIV_div[NearCLKDIV] * HSPCLKDIV_div[NearHSPCLKDIV]));
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const uint16_t shadow_mask = (REG16(baseAddr + AM335X_EPWM_TBCTL) &
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(~AM335X_EPWM_PRD_LOAD_SHADOW_MASK));
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const uint16_t shadow_disable = (((bool)AM335X_EPWM_SHADOW_WRITE_DISABLE <<
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AM335X_EPWM_TBCTL_PRDLD_SHIFT) & AM335X_EPWM_PRD_LOAD_SHADOW_MASK);
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REG16(baseAddr + AM335X_EPWM_TBCTL) = shadow_mask | shadow_disable;
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const uint16_t counter_mask = (REG16(baseAddr + AM335X_EPWM_TBCTL) &
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(~AM335X_EPWM_COUNTER_MODE_MASK));
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const uint16_t counter_shift = (((unsigned int)AM335X_EPWM_COUNT_UP <<
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AM335X_TBCTL_CTRMODE_SHIFT) & AM335X_EPWM_COUNTER_MODE_MASK);
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REG16(baseAddr + AM335X_EPWM_TBCTL) = counter_mask | counter_shift;
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/*setting clock divider and freeze time base*/
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REG16(baseAddr + AM335X_EPWM_CMPB) = (unsigned short)((float)(NearTBPRD) * duty_b);
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REG16(baseAddr + AM335X_EPWM_CMPA) = (unsigned short)((float)(NearTBPRD) * duty_a);
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REG16(baseAddr + AM335X_EPWM_TBPRD) = (unsigned short)NearTBPRD;
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REG16(baseAddr + AM335X_EPWM_TBCNT) = 0;
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}
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return status;
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}
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bool beagle_pwm_enable(BBB_PWMSS pwmid)
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{
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const bool id_is_valid = pwmid < BBB_PWMSS_COUNT;
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bool status = true;
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if (id_is_valid) {
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const uint32_t baseAddr = select_pwm(pwmid);
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/* Initially set EPWMxA o/p high , when increasing counter = CMPA toggle o/p of EPWMxA */
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REG16(baseAddr + AM335X_EPWM_AQCTLA) = AM335X_EPWM_AQCTLA_ZRO_XAHIGH | (AM335X_EPWM_AQCTLA_CAU_EPWMXATOGGLE << AM335X_EPWM_AQCTLA_CAU_SHIFT);
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/* Initially set EPWMxB o/p high , when increasing counter = CMPA toggle o/p of EPWMxB */
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REG16(baseAddr + AM335X_EPWM_AQCTLB) = AM335X_EPWM_AQCTLB_ZRO_XBHIGH | (AM335X_EPWM_AQCTLB_CBU_EPWMXBTOGGLE << AM335X_EPWM_AQCTLB_CBU_SHIFT);
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REG16(baseAddr + AM335X_EPWM_TBCNT) = 0;
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/* Set counter mode : Up-count mode */
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REG16(baseAddr + AM335X_EPWM_TBCTL) |= AM335X_TBCTL_FREERUN | AM335X_TBCTL_CTRMODE_UP;
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} else {
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status =false;
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}
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return status;
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}
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bool beagle_pwm_disable(BBB_PWMSS pwmid)
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{
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const bool id_is_valid = pwmid < BBB_PWMSS_COUNT;
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bool status = true;
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if (id_is_valid) {
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const uint32_t baseAddr = select_pwm(pwmid);
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REG16(baseAddr + AM335X_EPWM_TBCTL) = AM335X_EPWM_TBCTL_CTRMODE_STOPFREEZE;
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REG16(baseAddr + AM335X_EPWM_AQCTLA) = AM335X_EPWM_AQCTLA_ZRO_XALOW | (AM335X_EPWM_AQCTLA_CAU_EPWMXATOGGLE << AM335X_EPWM_AQCTLA_CAU_SHIFT);
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REG16(baseAddr + AM335X_EPWM_AQCTLB) = AM335X_EPWM_AQCTLA_ZRO_XBLOW | (AM335X_EPWM_AQCTLB_CBU_EPWMXBTOGGLE << AM335X_EPWM_AQCTLB_CBU_SHIFT);
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REG16(baseAddr + AM335X_EPWM_TBCNT) = 0;
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} else {
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status = false;
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}
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return status;
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}
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/**
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* @brief This functions determines whether time base clock is enabled for EPWMSS
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*
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* @param pwmss_id The instance number of ePWMSS whose time base clock need to
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* be checked
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*
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* @return returns 4 for PWMSS_ID = 2
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* returns 2 for PWMSS_ID = 1
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* returns 1 for PWMSS_ID = 0
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**/
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static int pwmss_tb_clock_check(unsigned int pwmss_id)
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{
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unsigned int reg_value;
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/*control module check*/
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reg_value = REG(AM335X_CONTROL_MODULE + AM335X_PWMSS_CTRL);
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return (reg_value & (1 << pwmss_id));
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}
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/**
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* @brief This functions determines whether clock for EPWMSS is enabled or not.
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*
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* @param It is the Memory address of the PWMSS instance used.
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*
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* @return
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*
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**/
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static unsigned int pwmss_clock_en_status(unsigned int pwmid)
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{
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unsigned int status;
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const uint32_t baseAddr = select_pwmss(pwmid);
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status = REG(baseAddr + AM335X_PWMSS_CLKSTATUS);
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status = status >> 8 & 0x1;
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return status;
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}
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bool beagle_pwmss_is_running(unsigned int pwmss_id)
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{
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const bool id_is_valid = pwmss_id < BBB_PWMSS_COUNT;
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bool status=true;
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if (id_is_valid) {
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status = pwmss_clock_en_status(pwmss_id);
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if(status){
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status = pwmss_tb_clock_check(pwmss_id);
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} else {
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status = false;
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}
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} else {
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status = false;
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}
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return status;
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}
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#endif
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/* For support of BeagleboardxM */
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#if IS_DM3730
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/* Currently this section is just to satisfy
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* GPIO API and to make the build successful.
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* Later on support can be added here.
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*/
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bool beagle_pwm_init(BBB_PWMSS pwmss_id)
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{
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return false;
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}
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bool beagle_pwm_disable(BBB_PWMSS pwmid)
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{
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return false;
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}
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bool beagle_pwm_enable(BBB_PWMSS pwmid)
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{
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return false;
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}
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int beagle_pwm_configure(BBB_PWMSS pwm_id, float pwm_freq, float duty_a, float duty_b)
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{
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return -1;
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}
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bool beagle_pwm_pinmux_setup(bbb_pwm_pin_t pin_no, BBB_PWMSS pwm_id)
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{
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return false;
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}
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bool beagle_pwmss_is_running(unsigned int pwmss_id)
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{
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return false;
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}
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#endif
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