forked from Imagelibrary/rtems
599 lines
13 KiB
ArmAsm
599 lines
13 KiB
ArmAsm
/**
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* @file
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*
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* @brief Boot and system start code.
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*/
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/*
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* Copyright (C) 2008, 2020 embedded brains GmbH & Co. KG
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*
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* Copyright (c) 2016 Pavel Pisa <pisa@cmp.felk.cvut.cz>
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*
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* Czech Technical University in Prague
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* Zikova 1903/4
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* 166 36 Praha 6
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* Czech Republic
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#include <rtems/asm.h>
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#include <rtems/score/percpu.h>
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#include <bspopts.h>
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#include <bsp/irq.h>
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#include <dev/cache/arm-data-cache-loop-set-way.h>
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/* Global symbols */
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.globl _start
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.type _start, %function
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.globl bsp_start_hook_0_done
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.type bsp_start_hook_0_done, %function
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.globl bsp_start_vector_table_begin
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.globl bsp_start_vector_table_end
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.globl bsp_start_vector_table_size
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.globl bsp_vector_table_size
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.section ".bsp_start_text", "ax"
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#ifdef BSP_START_ZIMAGE_HEADER
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.rept 8
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mov r0, r0
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.endr
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b .Lafter_header
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.word 0x016f2818 /* Magic numbers to help the loader */
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.word bsp_section_start_begin /* zImage start address */
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.word bsp_section_data_end /* zImage end address */
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.Lafter_header:
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#endif /* BSP_START_ZIMAGE_HEADER */
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#if defined(ARM_MULTILIB_ARCH_V4)
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#ifdef BSP_START_IN_HYP_SUPPORT
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.globl bsp_start_hyp_vector_table_begin
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#endif
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.arm
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/*
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* This is the exception vector table and the pointers to the default
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* exceptions handlers.
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*/
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bsp_start_vector_table_begin:
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ldr pc, .Lhandler_addr_reset
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ldr pc, .Lhandler_addr_undef
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ldr pc, .Lhandler_addr_swi
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ldr pc, .Lhandler_addr_prefetch
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ldr pc, .Lhandler_addr_abort
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/* Program signature checked by boot loader */
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.word 0xb8a06f58
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ldr pc, .Lhandler_addr_irq
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ldr pc, .Lhandler_addr_fiq
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.Lhandler_addr_reset:
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#ifdef BSP_START_RESET_VECTOR
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.word BSP_START_RESET_VECTOR
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#else
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.word _start
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#endif
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.Lhandler_addr_undef:
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.word _ARMV4_Exception_undef_default
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.Lhandler_addr_swi:
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.word _ARMV4_Exception_swi_default
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.Lhandler_addr_prefetch:
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.word _ARMV4_Exception_pref_abort_default
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.Lhandler_addr_abort:
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.word _ARMV4_Exception_data_abort_default
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.Lhandler_addr_reserved:
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.word _ARMV4_Exception_reserved_default
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.Lhandler_addr_irq:
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.word _ARMV4_Exception_interrupt
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.Lhandler_addr_fiq:
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.word _ARMV4_Exception_fiq_default
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bsp_start_vector_table_end:
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#ifdef BSP_START_IN_HYP_SUPPORT
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bsp_start_hyp_vector_table_begin:
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ldr pc, .Lhandler_addr_hyp_reset
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ldr pc, .Lhandler_addr_hyp_undef
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ldr pc, .Lhandler_addr_hyp_swi
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ldr pc, .Lhandler_addr_hyp_prefetch
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ldr pc, .Lhandler_addr_hyp_abort
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ldr pc, .Lhandler_addr_hyp_hyp
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ldr pc, .Lhandler_addr_hyp_irq
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ldr pc, .Lhandler_addr_hyp_fiq
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.Lhandler_addr_hyp_reset:
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.word _ARMV4_Exception_reserved_default
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.Lhandler_addr_hyp_undef:
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.word _ARMV4_Exception_reserved_default
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.Lhandler_addr_hyp_swi:
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.word _ARMV4_Exception_reserved_default
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.Lhandler_addr_hyp_prefetch:
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.word _ARMV4_Exception_reserved_default
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.Lhandler_addr_hyp_abort:
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.word _ARMV4_Exception_reserved_default
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.Lhandler_addr_hyp_hyp:
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.word _ARMV4_Exception_reserved_default
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.Lhandler_addr_hyp_irq:
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.word _ARMV4_Exception_reserved_default
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.Lhandler_addr_hyp_fiq:
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.word _ARMV4_Exception_reserved_default
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#endif
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/* Start entry */
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_start:
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/*
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* We do not save the context since we do not return to the boot
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* loader. Boot loaders may pass the device tree in r2. Do not touch
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* r2 until bsp_fdt_copy() is called.
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*/
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#ifdef BSP_START_NEEDS_REGISTER_INITIALIZATION
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mov r0, #0
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mov r1, #0
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mov r2, #0
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mov r3, #0
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mov r4, #0
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mov r5, #0
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mov r6, #0
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mov r7, #0
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mov r8, #0
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mov r9, #0
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mov r10, #0
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mov r11, #0
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mov r12, #0
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mov r13, #0
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#endif
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#if __ARM_ARCH >= 7
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/*
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* Write to BPIALL (Branch Predictor Invalidate All) to invalidate all
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* branch predictors. There is no need to use BPIALLIS (Branch
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* Predictor Invalidate All, Inner Shareable) since this code is
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* executed on all processors used by RTEMS.
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*/
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 6
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#endif
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#ifdef RTEMS_SMP
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/* Read MPIDR and get current processor index */
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mrc p15, 0, r7, c0, c0, 5
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and r7, #0xff
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/*
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* Check that this is a configured processor. If not, then there is
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* not much that can be done since we do not have a stack available for
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* this processor. Just loop forever in this case.
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*/
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ldr r1, =_SMP_Processor_configured_maximum
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ldr r1, [r1]
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cmp r1, r7
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bgt .Lconfigured_processor
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.Linvalid_processor_wait_for_ever:
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wfe
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b .Linvalid_processor_wait_for_ever
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.Lconfigured_processor:
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/*
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* Get current per-CPU control and store it in PL1 only Thread ID
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* Register (TPIDRPRW).
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*/
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ldr r1, =_Per_CPU_Information
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add r1, r1, r7, asl #PER_CPU_CONTROL_SIZE_LOG2
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mcr p15, 0, r1, c13, c0, 4
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#endif
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/* Calculate interrupt stack area end for current processor */
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ldr r1, =_ISR_Stack_size
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#ifdef RTEMS_SMP
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add r3, r7, #1
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mul r1, r1, r3
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#endif
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ldr r0, =_ISR_Stack_area_begin
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add r3, r1, r0
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/* Save original CPSR value */
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mrs r4, cpsr
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#ifdef BSP_START_IN_HYP_SUPPORT
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orr r0, r4, #(ARM_PSR_I | ARM_PSR_F)
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msr cpsr, r4
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and r0, r4, #ARM_PSR_M_MASK
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cmp r0, #ARM_PSR_M_HYP
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bne .L_skip_hyp_svc_switch
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/* Boot loader starts kernel in HYP mode, switch to SVC necessary */
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ldr r1, =bsp_stack_hyp_size
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mov sp, r3
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sub r3, r3, r1
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ldr r0, =bsp_start_hyp_vector_table_begin
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mcr p15, 4, r0, c12, c0, 0
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mov r0, #0
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mcr p15, 4, r0, c1, c1, 0
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mcr p15, 4, r0, c1, c1, 2
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mcr p15, 4, r0, c1, c1, 3
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/*
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* HSCTLR.TE
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* optional start of hypervisor handlers in Thumb mode
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* orr r0, #(1 << 30)
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*/
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mcr p15, 4, r0, c1, c0, 0 /* HSCTLR */
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mrc p15, 4, r0, c1, c1, 1 /* HDCR */
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and r0, #0x1f /* Preserve HPMN */
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mcr p15, 4, r0, c1, c1, 1 /* HDCR */
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/* Prepare SVC mode for eret */
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mrs r0, cpsr
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bic r0, r0, #ARM_PSR_M_MASK
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orr r0, r0, #ARM_PSR_M_SVC
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msr spsr_cxsf, r0
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ldr r0, =.L_hyp_to_svc_return
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.inst 0xe12ef300 /* msr ELR_hyp, r0 */
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mov r0, sp
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.inst 0xe160006e /* eret */
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.L_hyp_to_svc_return:
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mov sp, r0
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.L_skip_hyp_svc_switch:
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#endif /* BSP_START_IN_HYP_SUPPORT */
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/* Initialize stack pointer registers for the various modes */
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/* Enter FIQ mode and set up the FIQ stack pointer */
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mov r0, #(ARM_PSR_M_FIQ | ARM_PSR_I | ARM_PSR_F)
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msr cpsr, r0
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ldr r1, =bsp_stack_fiq_size
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mov sp, r3
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sub r3, r3, r1
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#ifdef BSP_START_NEEDS_REGISTER_INITIALIZATION
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/* These are banked FIQ mode registers */
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mov r8, #0
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mov r9, #0
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mov r10, #0
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mov r11, #0
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mov r12, #0
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#endif
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/* Enter ABT mode and set up the ABT stack pointer */
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mov r0, #(ARM_PSR_M_ABT | ARM_PSR_I | ARM_PSR_F)
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msr cpsr, r0
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ldr r1, =bsp_stack_abt_size
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mov sp, r3
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sub r3, r3, r1
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/* Enter UND mode and set up the UND stack pointer */
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mov r0, #(ARM_PSR_M_UND | ARM_PSR_I | ARM_PSR_F)
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msr cpsr, r0
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ldr r1, =bsp_stack_und_size
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mov sp, r3
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sub r3, r3, r1
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/* Enter IRQ mode and set up the IRQ stack pointer */
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mov r0, #(ARM_PSR_M_IRQ | ARM_PSR_I | ARM_PSR_F)
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msr cpsr, r0
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mov sp, r3
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/*
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* Enter SVC mode and set up the SVC stack pointer, reuse IRQ stack
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* (interrupts are disabled).
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*/
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mov r0, #(ARM_PSR_M_SVC | ARM_PSR_I | ARM_PSR_F)
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msr cpsr, r0
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mov sp, r3
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/* Stay in SVC mode */
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/* Copy device tree from boot loader */
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#ifdef BSP_START_COPY_FDT_FROM_U_BOOT
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#ifdef RTEMS_SMP
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cmp r7, #0
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bne 1f
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#endif
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mov r0, r2
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bl bsp_fdt_copy
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1:
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#endif
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#ifdef ARM_MULTILIB_VFP
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#ifdef ARM_MULTILIB_HAS_CPACR
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/* Read CPACR */
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mrc p15, 0, r0, c1, c0, 2
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/* Enable CP10 and CP11 */
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orr r0, r0, #(1 << 20)
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orr r0, r0, #(1 << 22)
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/*
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* Clear ASEDIS and D32DIS. Writes to D32DIS are ignored for VFP-D16.
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*/
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bic r0, r0, #(3 << 30)
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/* Write CPACR */
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mcr p15, 0, r0, c1, c0, 2
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isb
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#endif
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/* Enable FPU */
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mov r0, #(1 << 30)
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vmsr FPEXC, r0
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#ifdef BSP_START_NEEDS_REGISTER_INITIALIZATION
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mov r0, #0
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vmov d0, r0, r0
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vmov d1, r0, r0
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vmov d2, r0, r0
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vmov d3, r0, r0
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vmov d4, r0, r0
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vmov d5, r0, r0
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vmov d6, r0, r0
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vmov d7, r0, r0
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vmov d8, r0, r0
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vmov d9, r0, r0
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vmov d10, r0, r0
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vmov d11, r0, r0
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vmov d12, r0, r0
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vmov d13, r0, r0
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vmov d14, r0, r0
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vmov d15, r0, r0
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#ifdef ARM_MULTILIB_VFP_D32
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vmov d16, r0, r0
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vmov d17, r0, r0
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vmov d18, r0, r0
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vmov d19, r0, r0
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vmov d20, r0, r0
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vmov d21, r0, r0
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vmov d22, r0, r0
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vmov d23, r0, r0
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vmov d24, r0, r0
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vmov d25, r0, r0
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vmov d26, r0, r0
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vmov d27, r0, r0
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vmov d28, r0, r0
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vmov d29, r0, r0
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vmov d30, r0, r0
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vmov d31, r0, r0
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#endif /* ARM_MULTILIB_VFP_D32 */
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#endif /* BSP_START_NEEDS_REGISTER_INITIALIZATION */
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#endif /* ARM_MULTILIB_VFP */
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#if (__ARM_ARCH >= 7 && __ARM_ARCH_PROFILE == 'A') || __ARM_ARCH >= 8
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/*
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* Set VBAR to the vector table in the start section and make sure
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* SCTLR[M, I, A, C, V] are cleared. Afterwards, exceptions are
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* handled by RTEMS.
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*/
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ldr r0, =bsp_start_vector_table_begin
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dsb
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mcr p15, 0, r0, c12, c0, 0
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mrc p15, 0, r0, c1, c0, 0
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bic r1, r0, #0x2800
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bic r1, r1, #0x7
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mcr p15, 0, r1, c1, c0, 0
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isb
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#ifdef RTEMS_SMP
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/* Skip the data cache initialization if we are a secondary processor */
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cmp r7, #0
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bne .Ldata_caches_initialized
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#endif
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/* Check previous SCTLR[C] and initialize data caches */
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tst r0, #0x4
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bne .Lclean_invalidate_data_caches
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/*
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* Invalidate the sets and ways of all data or unified cache levels
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* using DCISW (Data Cache line Invalidate by Set/Way).
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*/
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ARM_DATA_CACHE_LOOP_SET_WAY c6
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b .Ldata_caches_initialized
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.Lclean_invalidate_data_caches:
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/*
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* Clean and invalidate the sets and ways of all data or unified cache
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* levels using DCCISW (Data Cache line Clean and Invalidate by
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* Set/Way).
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*/
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ARM_DATA_CACHE_LOOP_SET_WAY c14
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.Ldata_caches_initialized:
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/*
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* Invalidate the instruction cache levels using ICIALLU (Instruction
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* Cache Invalidate All to PoU).
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*/
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0
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#if __ARM_ARCH_PROFILE == 'A'
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/*
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* Invalidate the TLB using ITLBIALL (Instruction TLB Invalidate All).
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*/
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mov r0, #0
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mcr p15, 0, r0, c8, c7, 0
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isb
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#endif
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#endif /* (__ARM_ARCH >= 7 && __ARM_ARCH_PROFILE == 'A') || __ARM_ARCH >= 8 */
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/*
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* Invoke the start hook 0.
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*
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* The previous code and parts of the start hook 0 may run with an
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* address offset. After the return from start hook 0 it is assumed
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* that the code can run at its intended position. Thus the link
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* register will be loaded with the absolute address and the branch
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* link instruction cannot be used. In THUMB mode the branch
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* instruction as a very limited address range of 2KiB. Use a bx to
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* the start hook 0 address instead corrected by the address offset.
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*/
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ldr lr, =bsp_start_hook_0_done
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mov r0, pc
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ldr r1, =.Lget_absolute_pc
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.Lget_absolute_pc:
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sub r1, r0
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ldr r7, =bsp_start_hook_0
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add r7, r1
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bx r7
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/* Allow bsp_start_hook_0() hooks to jump to this label */
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bsp_start_hook_0_done:
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/*
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* Initialize the exception vectors. This includes the exceptions
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* vectors and the pointers to the default exception handlers.
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*/
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ldr r0, =bsp_vector_table_begin
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ldr r1, =bsp_start_vector_table_begin
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cmp r0, r1
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beq .Lvector_table_copy_done
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ldmia r1!, {r2-r9}
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stmia r0!, {r2-r9}
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ldmia r1!, {r2-r9}
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stmia r0!, {r2-r9}
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.Lvector_table_copy_done:
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/*
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* This code path is only executed by the primary processor. Set the
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* VBAR to the normal vector table. For secondary processors, this is
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* done by bsp_start_hook_0().
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*/
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#if (__ARM_ARCH >= 7 && __ARM_ARCH_PROFILE == 'A') || __ARM_ARCH >= 8
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ldr r0, =bsp_vector_table_begin
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dsb
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mcr p15, 0, r0, c12, c0, 0
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isb
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#elif defined(__ARM_ARCH_6KZ__)
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mov r1, #0
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ldr r0, =bsp_vector_table_begin
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mcr p15, 0, r1, c7, c10, 4 /* DataSync */
|
|
mcr p15, 0, r0, c12, c0, 0 /* Load VBAR */
|
|
mcr p15, 0, r1, c7, c5, 4 /* Flush Prefetch */
|
|
#endif
|
|
|
|
SWITCH_FROM_ARM_TO_THUMB r3
|
|
|
|
/* Branch to start hook 1 */
|
|
bl bsp_start_hook_1
|
|
|
|
/* Branch to boot card */
|
|
mov r0, #0
|
|
bl boot_card
|
|
|
|
#elif defined(ARM_MULTILIB_ARCH_V7M)
|
|
|
|
#include <rtems/score/armv7m.h>
|
|
|
|
.syntax unified
|
|
|
|
.thumb
|
|
|
|
bsp_start_vector_table_begin:
|
|
|
|
.word _ISR_Stack_area_end
|
|
.word _start /* Reset */
|
|
.word _ARMV7M_Exception_default /* NMI */
|
|
.word _ARMV7M_Exception_default /* Hard Fault */
|
|
.word _ARMV7M_Exception_default /* MPU Fault */
|
|
.word _ARMV7M_Exception_default /* Bus Fault */
|
|
.word _ARMV7M_Exception_default /* Usage Fault */
|
|
.word _ARMV7M_Exception_default /* Reserved */
|
|
.word _ARMV7M_Exception_default /* Reserved */
|
|
.word _ARMV7M_Exception_default /* Reserved */
|
|
.word _ARMV7M_Exception_default /* Reserved */
|
|
.word _ARMV7M_Supervisor_call /* SVC */
|
|
.word _ARMV7M_Exception_default /* Debug Monitor */
|
|
.word _ARMV7M_Exception_default /* Reserved */
|
|
.word _ARMV7M_Pendable_service_call /* PendSV */
|
|
.word _ARMV7M_Clock_handler /* SysTick */
|
|
.rept BSP_INTERRUPT_VECTOR_COUNT
|
|
.word _ARMV7M_NVIC_Interrupt_dispatch /* IRQ */
|
|
.endr
|
|
|
|
bsp_start_vector_table_end:
|
|
|
|
.thumb_func
|
|
|
|
_start:
|
|
|
|
#if defined(ARM_MULTILIB_VFP) && defined(ARM_MULTILIB_HAS_CPACR)
|
|
/*
|
|
* Enable CP10 and CP11 coprocessors for privileged and user mode in
|
|
* CPACR (bits 20-23). Ensure that write to register completes.
|
|
*/
|
|
ldr r0, =ARMV7M_CPACR
|
|
ldr r1, [r0]
|
|
orr r1, r1, #(0xf << 20)
|
|
str r1, [r0]
|
|
dsb
|
|
isb
|
|
#endif
|
|
|
|
ldr sp, =_ISR_Stack_area_end
|
|
|
|
/*
|
|
* Set the Main Stack Pointer (MSP) to the ISR stack area end just in
|
|
* case we run using the Process Stack Pointer (PSP).
|
|
*/
|
|
mov r0, sp
|
|
msr msp, r0
|
|
|
|
ldr lr, =bsp_start_hook_0_done + 1
|
|
b bsp_start_hook_0
|
|
|
|
/* Allow bsp_start_hook_0() hooks to jump to this label */
|
|
bsp_start_hook_0_done:
|
|
|
|
bl bsp_start_hook_1
|
|
movs r0, #0
|
|
bl boot_card
|
|
|
|
#endif /* defined(ARM_MULTILIB_ARCH_V7M) */
|
|
|
|
.set bsp_start_vector_table_size, bsp_start_vector_table_end - bsp_start_vector_table_begin
|
|
.set bsp_vector_table_size, bsp_start_vector_table_size
|