RTOS/rtems

Files

Chris Johns bc8ffae115 bsp/xilinx-zynq: Add devcfg and slcr drivers

The devfg driver loads the PL with a bitfile image. The driver can also
support scrubbing.

These drivers are from Patrick Gauvin <pggauvin at gmail.com> and a thread
on the devel list: https://lists.rtems.org/pipermail/devel/2017-May/017705.html

2024-10-30 23:04:42 +00:00

config

ZYNQ7000: Add support PYNQ, PicoZed, MicroZed, ZYBO and ZYBO Z7

2023-11-28 12:51:34 -06:00

console

dev/serial: Add Zynq UART kernel I/O support

2024-04-04 12:53:53 +02:00

dev

bsp/xilinx-zynq: Add devcfg and slcr drivers

2024-10-30 23:04:42 +00:00

include

bsp/xilinx-zynq: Add devcfg and slcr drivers

2024-10-30 23:04:42 +00:00

start

bsps/arm/zynq: Make secondary core wait on QEMU

2024-10-30 18:56:36 +00:00

README.md

bsp/arm/zynq: Move README to README.md

2024-04-26 08:01:52 +10:00

README.md

Xilinx Zynq Support

The Zynq is supports the common hard IP that is common to all versions of the Zynq device family.

MMU

To access the PL (FPGA Logic) create an MMU table in your application and create the entries that map to your FPGA IP.

QEMU

Tested only on Qemu.

git clone git://git.qemu.org/qemu.git qemu cd qemu git checkout 1b0d3845b454eaaac0b2064c78926ca4d739a080 mkdir build cd build ../configure --prefix=/opt/qemu --interp-prefix=/opt/qemu make make install export PATH="$PATH:/opt/qemu/bin"

qemu-system-arm -no-reboot -serial null -serial mon:stdio -net none -nographic -M xilinx-zynq-a9 -m 256M -kernel ticker.exe