forked from Imagelibrary/rtems
bc7313134f
The APIC timer is calibrated by running the i8254 PIT for a fraction of a second (determined by PIT_CALIBRATE_DIVIDER) and counting how many times the APIC counter has ticked. The calibration can be run multiple times (determined by APIC_TIMER_NUM_CALIBRATIONS) and averaged out. Updates #2898.
77 lines
2.6 KiB
C
77 lines
2.6 KiB
C
/*
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* Copyright (c) 2018.
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* Amaan Cheval <amaan.cheval@gmail.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <stdint.h>
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#include <rtems.h>
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#include <rtems/score/basedefs.h>
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#include <rtems/score/x86_64.h>
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#include <rtems/score/cpuimpl.h>
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#include <bsp/irq-generic.h>
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#include <pic.h>
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void pic_remap(uint8_t offset1, uint8_t offset2)
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{
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uint8_t a1, a2;
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/* save masks */
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a1 = inport_byte(PIC1_DATA);
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a2 = inport_byte(PIC2_DATA);
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/* start the initialization sequence in cascade mode */
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outport_byte(PIC1_COMMAND, PIC_ICW1_INIT | PIC_ICW1_ICW4);
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stub_io_wait();
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outport_byte(PIC2_COMMAND, PIC_ICW1_INIT | PIC_ICW1_ICW4);
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stub_io_wait();
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/* ICW2: Master PIC vector offset */
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outport_byte(PIC1_DATA, offset1);
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stub_io_wait();
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/* ICW2: Slave PIC vector offset */
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outport_byte(PIC2_DATA, offset2);
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stub_io_wait();
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/* ICW3: tell Master PIC that there is a slave PIC at IRQ2 (0000 0100) */
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outport_byte(PIC1_DATA, 4);
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stub_io_wait();
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/* ICW3: tell Slave PIC its cascade identity (0000 0010) */
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outport_byte(PIC2_DATA, 2);
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stub_io_wait();
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outport_byte(PIC1_DATA, PIC_ICW4_8086);
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stub_io_wait();
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outport_byte(PIC2_DATA, PIC_ICW4_8086);
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stub_io_wait();
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/* restore saved masks. */
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outport_byte(PIC1_DATA, a1);
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outport_byte(PIC2_DATA, a2);
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}
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void pic_disable(void)
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{
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/* Mask all lines on both master and slave PIC to disable */
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outport_byte(PIC1_DATA, 0xff);
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outport_byte(PIC2_DATA, 0xff);
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}
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