forked from Imagelibrary/rtems
146 lines
4.2 KiB
C
146 lines
4.2 KiB
C
/* SPDX-License-Identifier: BSD-2-Clause */
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/**
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* @file
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*
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* @ingroup RTEMSBSPsPowerPCMPC55XX
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*
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* @brief Clock and FMPLL configuration.
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*/
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/*
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* Copyright (c) 2008-2012 embedded brains GmbH. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <bsp/mpc55xx-config.h>
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const mpc55xx_clock_config mpc55xx_start_config_clock [1] = { {
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#ifdef MPC55XX_HAS_FMPLL
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.syncr_tmp = {
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.B = {
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.PREDIV = MPC55XX_FMPLL_PREDIV - 1,
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.MFD = MPC55XX_FMPLL_MFD,
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.RFD = 2,
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.LOCEN = 1
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}
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},
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.syncr_final = {
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.B = {
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.PREDIV = MPC55XX_FMPLL_PREDIV - 1,
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.MFD = MPC55XX_FMPLL_MFD,
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.RFD = 0,
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.LOCEN = 1,
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.LOLIRQ = 1,
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.LOCIRQ = 1
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}
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}
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#endif
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#ifdef MPC55XX_HAS_FMPLL_ENHANCED
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#define EPREDIV_VAL (MPC55XX_FMPLL_PREDIV-1)
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#define EMFD_VAL (MPC55XX_FMPLL_MFD-16)
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#define VCO_CLK_REF (MPC55XX_REFERENCE_CLOCK/(EPREDIV_VAL+1))
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#define VCO_CLK_OUT (VCO_CLK_REF*(EMFD_VAL+16))
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#define ERFD_VAL \
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(((VCO_CLK_OUT + MPC55XX_SYSTEM_CLOCK - 1) / MPC55XX_SYSTEM_CLOCK)-1)
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.esyncr2_tmp = {
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.B = {
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.LOCEN = 0,
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.LOLRE = 0,
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.LOCRE = 0,
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.LOLIRQ = 0,
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.LOCIRQ = 0,
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.ERATE = 0,
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.EDEPTH = 0,
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.ERFD = ERFD_VAL + 2 /* reduce output clock during init */
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}
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},
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.esyncr2_final = {
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.B = {
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.LOCEN = 0,
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.LOLRE = 0,
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.LOCRE = 0,
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.LOLIRQ = 0,
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.LOCIRQ = 0,
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.ERATE = 0,
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#if MPC55XX_CHIP_FAMILY == 567
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.CLKCFG_DIS = 1,
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#endif
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.EDEPTH = 0,
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.ERFD = ERFD_VAL /* nominal output clock after init */
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}
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},
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.esyncr1_final = {
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.B = {
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.CLKCFG = MPC55XX_FMPLL_ESYNCR1_CLKCFG,
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.EPREDIV = EPREDIV_VAL,
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.EMFD = EMFD_VAL
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}
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}
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#endif
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#ifdef MPC55XX_HAS_MODE_CONTROL
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.fmpll = {
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{
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.cr = {
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#if MPC55XX_REFERENCE_CLOCK == 8000000
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.B = { .IDF = 0, .ODF = 1, .NDIV = 60, .I_LOCK = 1, .PLL_ON = 1 }
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#elif MPC55XX_REFERENCE_CLOCK == 40000000
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.B = { .IDF = 3, .ODF = 1, .NDIV = 48, .I_LOCK = 1, .PLL_ON = 1 }
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#else
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#error "unexpected reference clock"
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#endif
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}
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},
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{
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.cr = {
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.B = { .IDF = 3, .ODF = 2, .NDIV = 32, .I_LOCK = 1, .PLL_ON = 1 }
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}
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}
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},
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.ocds_sc = {
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.B = { .SELDIV = 2, .SELCTL = 2 }
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},
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.auxclk = {
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[0] = {
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.AC_SC = { .B = { .SELCTL = 4 } },
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.AC_DC0_3 = { .B = { .DE0 = 1, .DIV0 = 0 } }
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},
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[1] = {
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.AC_SC = { .B = { .SELCTL = 4 } },
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.AC_DC0_3 = { .B = { .DE0 = 1, .DIV0 = 11 } }
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},
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[2] = {
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.AC_SC = { .B = { .SELCTL = 4 } },
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.AC_DC0_3 = { .B = { .DE0 = 1, .DIV0 = 11 } }
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},
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[3] = {
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.AC_SC = { .B = { .SELCTL = 1 } }
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},
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[4] = {
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.AC_SC = { .B = { .SELCTL = 1 } }
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}
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}
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#endif
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} };
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