forked from Imagelibrary/rtems
114 lines
4.0 KiB
C
114 lines
4.0 KiB
C
/* SPDX-License-Identifier: BSD-2-Clause */
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/**
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* @file
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*
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* @ingroup RTEMSBSPsPowerPCMPC55XX
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*
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* @brief Register definitions.
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*/
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/*
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* Copyright (c) 2008-2014 embedded brains GmbH. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef LIBCPU_POWERPC_MPC55XX_REG_DEFS_H
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#define LIBCPU_POWERPC_MPC55XX_REG_DEFS_H
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#include <bspopts.h>
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#if MPC55XX_CHIP_FAMILY == 551
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#define FLASH_BIUCR 0xFFFF801C
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#else
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#define FLASH_BIUCR 0xC3F8801C
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#endif
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/*
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* Definitions for FLASH_BIUCR (Flash BIU Control Register)
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*/
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/* Fields for Flash Bus Interface Control */
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/* Fields for Prefetch Control (MnPFE Master n Prefetch Enable) */
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/* Fields for M3PFE (Master 3 (EBI) prefetch enable bit [12]) */
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#define FLASH_BUICR_EBI_PREFTCH 0x00080000
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/* Fields for M2PFE (Master 2 (eDMA) prefetch enable bit [13]) */
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#define FLASH_BUICR_EDMA_PREFTCH 0x00040000
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/* Fields for M1PFE (Master 1 (Nexus) prefetch enable bit [14]) */
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#define FLASH_BUICR_NEX_PREFTCH 0x00020000
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/* Fields for M0PFE (Master 0 (e200z core) prefetch enable bit [15]) */
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#define FLASH_BUICR_CPU_PREFTCH 0x00010000
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/* Fields for APC (access pipelining control bits [16:18]) */
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#define FLASH_BUICR_APC_0 0x00000000
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#define FLASH_BUICR_APC_1 0x00002000
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#define FLASH_BUICR_APC_2 0x00004000
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#define FLASH_BUICR_APC_3 0x00006000
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#define FLASH_BUICR_APC_4 0x00008000
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#define FLASH_BUICR_APC_5 0x0000A000
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#define FLASH_BUICR_APC_6 0x0000C000
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#define FLASH_BUICR_APC_NO 0x0000E000
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/* Fields for WWSC (write wait state control bits [19:20]) */
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#define FLASH_BUICR_WWSC_1 0x00000800
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#define FLASH_BUICR_WWSC_2 0x00001000
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#define FLASH_BUICR_WWSC_3 0x00001800
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/* Fields for RWSC (read wait state control bits [21:23]) */
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#define FLASH_BUICR_RWSC_0 0x00000000
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#define FLASH_BUICR_RWSC_1 0x00000100
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#define FLASH_BUICR_RWSC_2 0x00000200
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#define FLASH_BUICR_RWSC_3 0x00000300
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#define FLASH_BUICR_RWSC_4 0x00000400
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#define FLASH_BUICR_RWSC_5 0x00000500
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#define FLASH_BUICR_RWSC_6 0x00000600
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#define FLASH_BUICR_RWSC_7 0x00000700
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/* Fields for DPFEN (data prefetch enable bits [24:25]) */
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#define FLASH_BUICR_DPFEN_0 0x00000000
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#define FLASH_BUICR_DPFEN_1 0x00000040
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#define FLASH_BUICR_DPFEN_3 0x000000C0
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/* Fields for IPFEN (instruction prefetch enable bits [26:27]) */
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#define FLASH_BUICR_IPFEN_0 0x00000000
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#define FLASH_BUICR_IPFEN_1 0x00000010
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#define FLASH_BUICR_IPFEN_3 0x00000030
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/* Fields for PFLIM (additional line prefetch (limit) bits [28:30]) */
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#define FLASH_BUICR_PFLIM_0 0x00000000
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#define FLASH_BUICR_PFLIM_1 0x00000002
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#define FLASH_BUICR_PFLIM_2 0x00000004
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#define FLASH_BUICR_PFLIM_3 0x00000006
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#define FLASH_BUICR_PFLIM_4 0x00000008
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#define FLASH_BUICR_PFLIM_5 0x0000000A
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#define FLASH_BUICR_PFLIM_6 0x0000000C
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/* Fields for BFEN (enable line read buffer hits bit [31]) */
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#define FLASH_BUICR_BFEN 0x00000001
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#endif /* LIBCPU_POWERPC_MPC55XX_REG_DEFS_H */
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