forked from Imagelibrary/rtems
42 lines
1.4 KiB
C
42 lines
1.4 KiB
C
/*
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* Copyright (c) 2017 embedded brains GmbH. All rights reserved.
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#include <bsp/atsam-clock-config.h>
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#include <bspopts.h>
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#include <chip.h>
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#if ATSAM_MCK == 123000000
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/* PLLA/HCLK/MCK clock is set to 492/246/123MHz */
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const struct atsam_clock_config atsam_clock_config = {
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.pllar_init = (CKGR_PLLAR_ONE | CKGR_PLLAR_MULA(0x28U) |
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CKGR_PLLAR_PLLACOUNT(0x3fU) | CKGR_PLLAR_DIVA(0x1U)),
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.mckr_init = (PMC_MCKR_PRES_CLK_2 | PMC_MCKR_CSS_PLLA_CLK |
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PMC_MCKR_MDIV_PCK_DIV2),
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.mck_freq = 123*1000*1000
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};
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#elif ATSAM_MCK == 150000000
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/* PLLA/HCLK/MCK clock is set to 300/300/150MHz */
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const struct atsam_clock_config atsam_clock_config = {
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.pllar_init = (CKGR_PLLAR_ONE | CKGR_PLLAR_MULA(0x18U) |
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CKGR_PLLAR_PLLACOUNT(0x3fU) | CKGR_PLLAR_DIVA(0x1U)),
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.mckr_init = (PMC_MCKR_PRES_CLK_1 | PMC_MCKR_CSS_PLLA_CLK |
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PMC_MCKR_MDIV_PCK_DIV2),
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.mck_freq = 150*1000*1000
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};
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#elif ATSAM_MCK == 60000000
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/* PLLA/HCLK/MCK clock is set to 60/60/60MHz */
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const struct atsam_clock_config atsam_clock_config = {
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.pllar_init = (CKGR_PLLAR_ONE | CKGR_PLLAR_MULA(0x4U) |
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CKGR_PLLAR_PLLACOUNT(0x3fU) | CKGR_PLLAR_DIVA(0x1U)),
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.mckr_init = (PMC_MCKR_PRES_CLK_1 | PMC_MCKR_CSS_PLLA_CLK |
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PMC_MCKR_MDIV_EQ_PCK),
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.mck_freq = 60*1000*1000
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};
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#error Unknown ATSAM_MCK.
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#endif
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