forked from Imagelibrary/rtems
9a12fdff51
* asm.h, cpu.c, cpu_asm.S, rtems/score/arm.h, rtems/score/cpu.h, rtems/score/cpu_asm.h, rtems/score/types.h: URL for license changed.
155 lines
4.2 KiB
ArmAsm
155 lines
4.2 KiB
ArmAsm
/*
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* $Id$
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*
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* This file contains all assembly code for the ARM implementation
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* of RTEMS.
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*
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* Copyright (c) 2002 by Advent Networks, Inc.
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* Jay Monkman <jmonkman@adventnetworks.com>
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*
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* COPYRIGHT (c) 2000 Canon Research Centre France SA.
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* Emmanuel Raguet, mailto:raguet@crf.canon.fr
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.com/license/LICENSE.
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*
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*/
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#include <asm.h>
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#include <rtems/score/cpu_asm.h>
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/*
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* void _CPU_Context_switch( run_context, heir_context )
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* void _CPU_Context_restore( run_context, heir_context )
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*
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* This routine performs a normal non-FP context.
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*
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* R0 = run_context R1 = heir_context
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*
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* This function copies the current registers to where r0 points, then
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* restores the ones from where r1 points.
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*
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* Using the ldm/stm opcodes save 2-3 us on 100 MHz ARM9TDMI with
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* a 16 bit data bus.
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*
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*/
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.globl _CPU_Context_switch
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_CPU_Context_switch:
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/* Start saving context */
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mrs r2, cpsr
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stmia r0, {r2, r4, r5, r6, r7, r8, r9, r10, r11, r13, r14}
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/* Start restoring context */
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_restore:
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ldmia r1, {r2, r4, r5, r6, r7, r8, r9, r10, r11, r13, r14}
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msr cpsr, r2
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mov pc, lr
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/*
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* void _CPU_Context_restore( new_context )
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*
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* This function copies the restores the registers from where r0 points.
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* It must match _CPU_Context_switch()
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*
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*/
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.globl _CPU_Context_restore
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_CPU_Context_restore:
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mov r1, r0
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b _restore
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/* FIXME: _Exception_Handler_Undef_Swi is untested */
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.globl _Exception_Handler_Undef_Swi
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_Exception_Handler_Undef_Swi:
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/* FIXME: This should use load and store multiple instructions */
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sub r13,r13,#SIZE_REGS
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str r4, [r13, #REG_R4]
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str r5, [r13, #REG_R5]
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str r6, [r13, #REG_R6]
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str r7, [r13, #REG_R7]
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str r8, [r13, #REG_R8]
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str r9, [r13, #REG_R9]
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str r10, [r13, #REG_R10]
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str r11, [r13, #REG_R11]
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str sp, [r13, #REG_SP]
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str lr, [r13, #REG_LR]
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mrs r0, cpsr /* read the status */
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and r0, r0,#0x1f /* we keep the mode as exception number */
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str r0, [r13, #REG_PC] /* we store it in a free place */
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mov r0, r13 /* put frame address in r0 (C arg 1) */
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ldr r1, =SWI_Handler
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ldr lr, =_go_back_1
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ldr pc,[r1] /* call handler */
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_go_back_1:
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ldr r4, [r13, #REG_R4]
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ldr r5, [r13, #REG_R5]
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ldr r6, [r13, #REG_R6]
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ldr r7, [r13, #REG_R7]
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ldr r8, [r13, #REG_R8]
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ldr r9, [r13, #REG_R9]
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ldr r10, [r13, #REG_R10]
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ldr r11, [r13, #REG_R11]
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ldr sp, [r13, #REG_SP]
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ldr lr, [r13, #REG_LR]
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add r13,r13,#SIZE_REGS
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movs pc,r14 /* return */
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/* FIXME: _Exception_Handler_Abort is untested */
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.globl _Exception_Handler_Abort
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_Exception_Handler_Abort:
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/* FIXME: This should use load and store multiple instructions */
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sub r13,r13,#SIZE_REGS
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str r4, [r13, #REG_R4]
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str r5, [r13, #REG_R5]
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str r6, [r13, #REG_R6]
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str r7, [r13, #REG_R7]
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str r8, [r13, #REG_R8]
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str r9, [r13, #REG_R9]
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str sp, [r13, #REG_R11]
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str lr, [r13, #REG_SP]
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str lr, [r13, #REG_LR]
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mrs r0, cpsr /* read the status */
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and r0, r0,#0x1f /* we keep the mode as exception number */
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str r0, [r13, #REG_PC] /* we store it in a free place */
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mov r0, r13 /* put frame address in ro (C arg 1) */
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ldr r1, =_currentExcHandler
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ldr lr, =_go_back_2
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ldr pc,[r1] /* call handler */
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_go_back_2:
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ldr r4, [r13, #REG_R4]
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ldr r5, [r13, #REG_R5]
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ldr r6, [r13, #REG_R6]
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ldr r7, [r13, #REG_R7]
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ldr r8, [r13, #REG_R8]
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ldr r9, [r13, #REG_R9]
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ldr r10, [r13, #REG_R10]
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ldr sp, [r13, #REG_R11]
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ldr lr, [r13, #REG_SP]
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ldr lr, [r13, #REG_LR]
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add r13,r13,#SIZE_REGS
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subs pc,r14,#4 /* return */
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.globl _exc_data_abort
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_exc_data_abort:
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sub sp, sp, #SIZE_REGS /* reserve register frame */
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stmia sp, {r0-r12}
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str lr, [sp, #REG_LR]
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mov r1, lr
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ldr r0, [r1, #-8] /* r0 = bad instruction */
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mrs r1, spsr /* r1 = spsr */
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mov r2, r13 /* r2 = exception frame */
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bl do_data_abort
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ldr lr, [sp, #REG_LR]
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ldmia sp, {r0-r12}
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add sp, sp, #SIZE_REGS
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subs pc, r14, #4 /* return to the instruction */
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/* _AFTER_ the aborted one */
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