forked from Imagelibrary/rtems
c4a3f1e914
* include/itron.h, include/itronsys/eventflags.h, include/itronsys/fmempool.h, include/itronsys/intr.h, include/itronsys/mbox.h, include/itronsys/msgbuffer.h, include/itronsys/network.h, include/itronsys/port.h, include/itronsys/semaphore.h, include/itronsys/status.h, include/itronsys/sysmgmt.h, include/itronsys/task.h, include/itronsys/time.h, include/itronsys/types.h, include/itronsys/vmempool.h, include/rtems/itron/config.h, include/rtems/itron/eventflags.h, include/rtems/itron/fmempool.h, include/rtems/itron/intr.h, include/rtems/itron/itronapi.h, include/rtems/itron/mbox.h, include/rtems/itron/msgbuffer.h, include/rtems/itron/network.h, include/rtems/itron/object.h, include/rtems/itron/port.h, include/rtems/itron/semaphore.h, include/rtems/itron/sysmgmt.h, include/rtems/itron/task.h, include/rtems/itron/time.h, include/rtems/itron/vmempool.h, inline/rtems/itron/eventflags.inl, inline/rtems/itron/fmempool.inl, inline/rtems/itron/intr.inl, inline/rtems/itron/mbox.inl, inline/rtems/itron/msgbuffer.inl, inline/rtems/itron/network.inl, inline/rtems/itron/port.inl, inline/rtems/itron/semaphore.inl, inline/rtems/itron/sysmgmt.inl, inline/rtems/itron/task.inl, inline/rtems/itron/time.inl, inline/rtems/itron/vmempool.inl, macros/rtems/itron/eventflags.inl, macros/rtems/itron/fmempool.inl, macros/rtems/itron/intr.inl, macros/rtems/itron/mbox.inl, macros/rtems/itron/msgbuffer.inl, macros/rtems/itron/network.inl, macros/rtems/itron/port.inl, macros/rtems/itron/semaphore.inl, macros/rtems/itron/sysmgmt.inl, macros/rtems/itron/task.inl, macros/rtems/itron/time.inl, macros/rtems/itron/vmempool.inl, src/can_wup.c, src/chg_pri.c, src/cre_mbf.c, src/cre_mbx.c, src/cre_sem.c, src/cre_tsk.c, src/del_mbf.c, src/del_mbx.c, src/del_sem.c, src/del_tsk.c, src/dis_dsp.c, src/ena_dsp.c, src/eventflags.c, src/exd_tsk.c, src/ext_tsk.c, src/fmempool.c, src/frsm_tsk.c, src/get_tid.c, src/itronintr.c, src/itronsem.c, src/itrontime.c, src/mbox.c, src/mboxtranslatereturncode.c, src/msgbuffer.c, src/msgbuffertranslatereturncode.c, src/network.c, src/port.c, src/prcv_mbf.c, src/prcv_mbx.c, src/preq_sem.c, src/psnd_mbf.c, src/rcv_mbf.c, src/rcv_mbx.c, src/ref_mbf.c, src/ref_mbx.c, src/ref_sem.c, src/ref_tsk.c, src/rel_wai.c, src/rot_rdq.c, src/rsm_tsk.c, src/sig_sem.c, src/slp_tsk.c, src/snd_mbf.c, src/snd_mbx.c, src/sta_tsk.c, src/sus_tsk.c, src/sysmgmt.c, src/task.c, src/ter_tsk.c, src/trcv_mbf.c, src/trcv_mbx.c, src/tslp_tsk.c, src/tsnd_mbf.c, src/twai_sem.c, src/vmempool.c, src/wai_sem.c, src/wup_tsk.c: URL for license changed.
320 lines
8.8 KiB
C
320 lines
8.8 KiB
C
/*
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* COPYRIGHT (c) 1989-1999.
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* On-Line Applications Research Corporation (OAR).
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.com/license/LICENSE.
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*
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* $Id$
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*/
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#ifndef __ITRON_SYSTEM_MANAGEMENT_h_
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#define __ITRON_SYSTEM_MANAGEMENT_h_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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* Get Version (get_ver) Structure
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*/
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typedef struct t_ver {
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UH maker; /* vendor */
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UH id; /* format number */
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UH spver; /* specification version */
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UH prver; /* product version */
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UH prno[4]; /* product control information */
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UH cpu; /* CPU information */
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UH var; /* variation descriptor */
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} T_VER;
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/*
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* Specific MAKER codes established as of March, 1993 are as follows.
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* Due to restrictions on the assignment of CPU codes described below, it is
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* necessary to use maker codes in the range 0x000 through 0x00ff for vendors
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* developing CPUs.
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*/
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/*
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* CPU defines XXX need to name the constants
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*/
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#if 0
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#define 0x000 /* No version (test systems, etc.) */
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#define 0x001 /* University of Tokyo */
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#define 0x009 /* FUJITSU LIMITED */
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#define 0x00a /* Hitachi, Ltd. */
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#define 0x00b /* Matsushita Electric Industrial Co., Ltd. */
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#define 0x00c /* Mitsubishi Electric Corporation */
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#define 0x00d /* NEC Corporation */
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#define 0x00e /* Oki Electric Industry Co., Ltd. */
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#define 0x00f /* TOSHIBA CORPORATION */
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#endif
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/*
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* The above have been assigned in alphabetical order.
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*/
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#if 0
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#define 0x010 /* ALPS ELECTRIC CO., LTD. */
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#define 0x011 /* WACOM Co., Ltd. */
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#define 0x012 /* Personal Media Corporation */
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#define 0x101 /* OMRON CORPORATION */
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#define 0x102 /* SEIKOSHA CO., LTD. */
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#define 0x103 /* SYSTEM ALGO CO., LTD. */
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#define 0x104 /* Tokyo Computer Service Co., Ltd. */
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#define 0x105 /* YAMAHA CORPORATION */
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#define 0x106 /* MORSON JAPAN */
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#define 0x107 /* TOSHIBA INFORMATION SYSTEMS (JAPAN) CORP. */
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#define 0x108 /* Miyazaki System Planning Office */
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#define 0x109 /* Three Ace Computer Corporation */
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#endif
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/*
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* CPU Codes
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*
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* Figure 47 shows the format of cpu code. Some processors use the format
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* given in Figure 47(1). The format given in Figure 47(2) is used for all
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* other proprietary processors.
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*
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* The code assignment of the CPU1 region in the format given in Figure 47(1)
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* is common to ITRON and BTRON specifications. The same number is used in
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* the CPU type of the standard object format of BTRON specification
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* operating systems implemented on a TRON-specification chip.
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*
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* When using the format given in Figure 47(2) the code used for MAKER1 is
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* assigned by using the lower 8 bits of MAKER described in the previous
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* subsection. The code assignment of CPU2 is left up to each maker.
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*
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*
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*
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* +---------------+---------------+---------------+---------------+
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* (1) | 0 0 0 0 0 0 0 0 | CPU1 |
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* +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
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* +---------------+---------------+---------------+---------------+
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* (2) | MAKER1 | CPU2 |
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* +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
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*
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* Figure 47 Format of cpu Returned by get_ver
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*
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*
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* Specific CPU codes established as of March, 1993 are as follows.
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*/
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#if 0
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/*
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* XXX CONVERT THESE to #defines
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*/
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/*
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* Contents of the CPU1 field
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*/
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#define (0x0) CPU unspecified, no CPU information given
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#define (0x1) TRONCHIP32 shared
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#define (0x2) reserved
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#define (0x3) reserved
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#define (0x4) reserved
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#define (0x5) reserved (<<L1R>> TRON-specification chip)
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#define (0x6) reserved (<<L1>> TRON-specification chip)
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#define (0x7) reserved (TRON-specification chip supporting the
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LSID function)
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/* CPU vendors are unspecified for codes B'00000000 through B'00000111. */
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#define (0x8) reserved
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#define (0x9) GMICRO/100
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#define (0xa) GMICRO/200
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#define (0xb) GMICRO/300
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#define (0xc) reserved
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#define (0xd) TX1
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#define (0xe) TX2
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#define (0xf) reserved
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#define (0x10) reserved
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#define (0x11) reserved
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#define (0x12) reserved
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#define (0x13) O32
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#define (0x14) reserved
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#define (0x15) MN10400
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#define (0x16) reserved
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#define (0x17) reserved
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#define (0x18) GMICRO/400
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#define (0x19) GMICRO/500
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#define (0x1a) reserved
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#define (0x1b-0x3f)
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reserved
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* For GMICRO extended, TX series extended, and TRONCHIP64 chips.
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#define (0x40) Motorola 68000
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#define (0x41) Motorola 68010
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#define (0x42) Motorola 68020
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#define (0x43) Motorola 68030
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#define (0x44) Motorola 68040
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#define -(0x40-0x4f)
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#define Motorola 68000 family
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#define (0x50) National Semiconductor NS32032
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#define (0x50-0x5f)
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National Semiconductor NS32000 family
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#define (0x60) Intel 8086, 8088
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#define (0x61) Intel 80186
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#define (0x62) Intel 80286
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#define (0x63) Intel 80386
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#define (0x64) Intel 80486
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#define (0x60-0x6f)
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Intel iAPX86 family
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#define (0x70-0x7f)
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NEC V Series
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#define (0x80-0xff)
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reserved
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#endif
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/*
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* Assigning Version Numbers
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*
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* The version numbers of ITRON and uITRON specifications take the following
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* form.
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*
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* Ver X.YY.ZZ[.WW]
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*
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* where "X" represents major version number of the ITRON specification to
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* distinguish ITRON1, ITRON2 and uITRON 3.0 specifications. Specific
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* assignment is as follows.
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*
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* "X" = 1 ITRON1 specification
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* = 2 ITRON2 or uITRON 2.0 specification
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* = 3 uITRON 3.0 specification
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*
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* "YY" is a number used to distinguish versions according to changes and
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* additions made to the specification. After the specification is published,
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* this number is incremented in order "YY" = 00, 01, 02... according to
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* version upgrades. The first digit of "YY" is 'A', 'B' or 'C' for draft
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* standard versions and test versions within the TRON Association before the
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* specification have been published.
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*
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* The "X.YY" part of the specification version numbers is returned by spver
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* to get_ver system call. The corresponding hexadecimal value is used when
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* "YY" includes 'A', 'B' or 'C'.
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*
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* "ZZ" represents a number used to distinguish versions related to the written
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* style of a specification. This number is incremented in order
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* "ZZ" = 00, 01, 02... when there have been changes in specification
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* configuration, reordering of chapters or corrections of misprints.
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* When a further distinction of the written style of specifications is
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* desired, ".WW" may be added optionally after "ZZ". WW will be assumed
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* to be zero if ".WW" is omitted.
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*/
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/*
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* Reference System (ref_sys) Structure
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*/
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typedef struct t_rsys {
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INT sysstat; /* system state */
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/* additional information may be included depending on the implementation */
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} T_RSYS;
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/*
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* sysstat
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*/
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#define TSS_TSK 0 /* normal state in which dispatching is enabled during
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task portion execution */
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#define TSS_DDSP 1 /* state after dis_dsp has been executed during task
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portion execution (dispatch disabled) */
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#define TSS_LOC 3 /* state after loc_cpu has been executed during task
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portion execution (interrupt and dispatch disabled)
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*/
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#define TSS_INDP 4 /* state during execution of task-independent portions
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(interrupt and timer handlers) */
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/*
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* Reference Configuration (ref_cfg) Structure
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*/
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typedef struct t_rcfg {
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/* details concerning members are implementation dependent */
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} T_RCFG;
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/*
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* Define Service (def_svc) Structure
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*/
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typedef struct t_dsvc {
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ATR svcatr; /* extended SVC handler attributes */
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FP svchdr; /* extended SVC handler address */
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/* additional information may be included depending on the implementation */
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} T_DSVC;
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/*
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* Define Exception (def_exc) Structure
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*/
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typedef struct t_dexc {
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ATR excatr; /* exception handler attributes */
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FP exchdr; /* exception handler address */
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/* additional information may be included depending on the implementation */
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} T_DEXC;
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/*
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* System Management Functions
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*/
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/*
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* get_ver - Get Version Information
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*/
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ER get_ver(
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T_VER *pk_ver
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);
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/*
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* ref_sys - Reference Semaphore Status
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*/
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ER ref_sys(
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T_RSYS *pk_rsys
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);
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/*
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* ref_cfg - Reference Configuration Information
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*/
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ER ref_cfg(
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T_RCFG *pk_rcfg
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);
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/*
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* def_svc - Define Extended SVC Handler
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*/
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ER def_svc(
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FN s_fncd,
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T_DSVC *pk_dsvc
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);
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/*
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* def_exc - Define Exception Handler
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*/
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ER def_exc(
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UINT exckind,
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T_DEXC *pk_dexc
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);
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#ifdef __cplusplus
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}
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#endif
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#endif
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/* end of include file */
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