forked from Imagelibrary/rtems
141 lines
3.0 KiB
C
141 lines
3.0 KiB
C
/**
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* @file
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*
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* @ingroup RTEMSBSPsARMLPC32XX
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*
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* @brief System clocks.
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*/
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/*
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* Copyright (c) 2011 embedded brains GmbH. All rights reserved.
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*
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* embedded brains GmbH
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* Obere Lagerstr. 30
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* 82178 Puchheim
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* Germany
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* <rtems@embedded-brains.de>
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#include <bsp.h>
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#include <bsp/lpc32xx.h>
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uint32_t lpc32xx_sysclk(void)
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{
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uint32_t sysclk_ctrl = LPC32XX_SYSCLK_CTRL;
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return (sysclk_ctrl & 0x1) == 0 ?
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LPC32XX_OSCILLATOR_MAIN
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: (397 * LPC32XX_OSCILLATOR_RTC);
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}
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uint32_t lpc32xx_hclkpll_clk(void)
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{
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uint32_t sysclk = lpc32xx_sysclk();
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uint32_t hclkpll_ctrl = LPC32XX_HCLKPLL_CTRL;
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uint32_t m = HCLK_PLL_M_GET(hclkpll_ctrl) + 1;
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uint32_t n = HCLK_PLL_N_GET(hclkpll_ctrl) + 1;
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uint32_t p = 1U << HCLK_PLL_P_GET(hclkpll_ctrl);
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uint32_t hclkpll_clk = 0;
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if ((hclkpll_ctrl & HCLK_PLL_BYPASS) != 0) {
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if ((hclkpll_ctrl & HCLK_PLL_DIRECT) != 0) {
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hclkpll_clk = sysclk;
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} else {
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hclkpll_clk = sysclk / (2 * p);
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}
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} else {
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if ((hclkpll_ctrl & HCLK_PLL_DIRECT) != 0) {
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hclkpll_clk = (m * sysclk) / n;
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} else {
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if ((hclkpll_ctrl & HCLK_PLL_FBD_FCLKOUT) != 0) {
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hclkpll_clk = m * (sysclk / n);
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} else {
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hclkpll_clk = (m / (2 * p)) * (sysclk / n);
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}
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}
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}
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return hclkpll_clk;
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}
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uint32_t lpc32xx_periph_clk(void)
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{
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uint32_t pwr_ctrl = LPC32XX_PWR_CTRL;
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uint32_t periph_clk = 0;
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if ((pwr_ctrl & PWR_NORMAL_RUN_MODE) != 0) {
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uint32_t hclkdiv_ctrl = LPC32XX_HCLKDIV_CTRL;
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uint32_t div = HCLK_DIV_PERIPH_CLK_GET(hclkdiv_ctrl) + 1;
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periph_clk = lpc32xx_hclkpll_clk() / div;
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} else {
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periph_clk = lpc32xx_sysclk();
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}
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return periph_clk;
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}
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uint32_t lpc32xx_hclk(void)
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{
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uint32_t pwr_ctrl = LPC32XX_PWR_CTRL;
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uint32_t hclk = 0;
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if ((pwr_ctrl & PWR_HCLK_USES_PERIPH_CLK) != 0) {
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hclk = lpc32xx_periph_clk();
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} else {
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if ((pwr_ctrl & PWR_NORMAL_RUN_MODE) != 0) {
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uint32_t hclkdiv_ctrl = LPC32XX_HCLKDIV_CTRL;
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uint32_t div = 1U << HCLK_DIV_HCLK_GET(hclkdiv_ctrl);
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hclk = lpc32xx_hclkpll_clk() / div;
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} else {
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hclk = lpc32xx_sysclk();
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}
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}
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return hclk;
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}
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uint32_t lpc32xx_arm_clk(void)
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{
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uint32_t pwr_ctrl = LPC32XX_PWR_CTRL;
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uint32_t arm_clk = 0;
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if ((pwr_ctrl & PWR_HCLK_USES_PERIPH_CLK) != 0) {
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arm_clk = lpc32xx_periph_clk();
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} else {
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if ((pwr_ctrl & PWR_NORMAL_RUN_MODE) != 0) {
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arm_clk = lpc32xx_hclkpll_clk();
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} else {
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arm_clk = lpc32xx_sysclk();
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}
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}
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return arm_clk;
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}
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uint32_t lpc32xx_ddram_clk(void)
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{
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uint32_t hclkdiv_ctrl = LPC32XX_HCLKDIV_CTRL;
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uint32_t div = HCLK_DIV_DDRAM_CLK_GET(hclkdiv_ctrl);
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uint32_t ddram_clk = 0;
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if (div != 0) {
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uint32_t pwr_ctrl = LPC32XX_PWR_CTRL;
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if ((pwr_ctrl & PWR_NORMAL_RUN_MODE) != 0) {
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ddram_clk = lpc32xx_hclkpll_clk();
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} else {
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ddram_clk = lpc32xx_sysclk();
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}
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ddram_clk /= div;
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}
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return ddram_clk;
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}
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