forked from Imagelibrary/rtems
c26259ee2e
Avoid reading from the pl011 data register unnecessarily. There is no need to preserve the contents of this register as it is not normal memory. This unnecessary read causes console spam when running under the Xen hypervisor when the read FIFO is empty since the read is not expected.
536 lines
14 KiB
C
536 lines
14 KiB
C
/* SPDX-License-Identifier: BSD-2-Clause */
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/*
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* Copyright (C) 2013, 2014 embedded brains GmbH & Co. KG
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <dev/serial/arm-pl011.h>
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#include <bspopts.h>
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static inline int arm_pl011_read_char(volatile pl011_base *regs_base)
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{
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return PL011_UARTDR_DATA_GET(regs_base->uartdr);
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}
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static inline void arm_pl011_write_char(
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volatile pl011_base *regs_base,
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const char ch
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)
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{
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regs_base->uartdr = PL011_UARTDR_DATA(ch);
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}
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static inline bool arm_pl011_is_rxfifo_empty(volatile pl011_base *regs_base)
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{
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return (regs_base->uartfr & PL011_UARTFR_RXFE) != 0;
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}
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static inline bool arm_pl011_is_txfifo_full(volatile pl011_base *regs_base)
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{
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return (regs_base->uartfr & PL011_UARTFR_TXFF) != 0;
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}
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volatile arm_pl011_uart *arm_pl011_get_regs(rtems_termios_device_context *base)
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{
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return ((arm_pl011_context *)base)->regs;
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}
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bool arm_pl011_probe(rtems_termios_device_context *base)
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{
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volatile arm_pl011_uart *regs = arm_pl011_get_regs(base);
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regs->base.uartlcr_h = PL011_UARTLCR_H_WLEN(PL011_UARTLCR_H_WLEN_8);
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regs->base.uartcr = PL011_UARTCR_RXE
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| PL011_UARTCR_TXE
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| PL011_UARTCR_UARTEN;
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return true;
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}
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static void arm_pl011_flush_fifos(const arm_pl011_context *context)
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{
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volatile pl011_base *regs = (volatile pl011_base *) context->regs;
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regs->uartlcr_h &= ~PL011_UARTLCR_H_FEN;
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regs->uartlcr_h |= PL011_UARTLCR_H_FEN;
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}
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#ifdef BSP_CONSOLE_USE_INTERRUPTS
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static inline void arm_pl011_clear_irq(
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volatile pl011_base *regs_base,
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const uint32_t irq_mask
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)
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{
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/* ICR is a write-only register */
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regs_base->uarticr = irq_mask;
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}
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static inline void arm_pl011_enable_irq(
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volatile pl011_base *regs_base,
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const uint32_t irq_mask
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)
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{
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regs_base->uartimsc |= irq_mask;
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}
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#endif
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static inline void arm_pl011_disable_irq(
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volatile pl011_base *regs_base,
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uint32_t irq_mask
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)
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{
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regs_base->uartimsc &= ~irq_mask;
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}
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#ifdef BSP_CONSOLE_USE_INTERRUPTS
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static void arm_pl011_irq_handler(void *arg)
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{
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arm_pl011_context *context = (void *) arg;
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volatile arm_pl011_uart *regs =
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arm_pl011_get_regs((rtems_termios_device_context *) context);
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const uint32_t irqs = regs->base.uartmis;
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char buffer[ARM_PL011_FIFO_DEPTH];
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/* RXFIFO got data */
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uint32_t rx_irq_mask = PL011_UARTI_RTI | PL011_UARTI_RXI;
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if ((irqs & rx_irq_mask) != 0) {
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arm_pl011_clear_irq(®s->base, rx_irq_mask);
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unsigned int i = 0;
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while (i < sizeof(buffer) && !arm_pl011_is_rxfifo_empty(®s->base)) {
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buffer[i] = arm_pl011_read_char(®s->base);
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i++;
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}
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(void) rtems_termios_enqueue_raw_characters(context->tty, buffer, i);
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}
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/*
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* Some characters got queued in the TXFIFO, so dequeue them from Termios'
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* structures.
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*/
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if ((irqs & PL011_UARTI_TXI) != 0) {
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/*
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* First interrupt was raised, so no need to trigger the handler
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* through software anymore.
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*/
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if (context->needs_sw_triggered_tx_irq == true) {
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context->needs_sw_triggered_tx_irq = false;
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}
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(void) rtems_termios_dequeue_characters(context->tty,
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context->tx_queued_chars);
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/*
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* Explicitly clear the transmit interrupt. This is necessary
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* because there may not be enough bytes in the output buffer to
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* fill the FIFO greater than the transmit interrupt trigger level.
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* If FIFOs are disabled, this applies if there are 0 bytes to
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* transmit and therefore nothing to fill the Tx holding register
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* with.
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*/
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arm_pl011_clear_irq(®s->base, PL011_UARTI_TXI);
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}
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}
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static bool arm_pl011_first_open_irq(
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rtems_termios_device_context *base,
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arm_pl011_context *context
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)
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{
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rtems_status_code sc;
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volatile arm_pl011_uart *regs = arm_pl011_get_regs(base);
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/* Set FIFO trigger levels for interrupts */
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regs->base.uartifls =
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PL011_UARTIFLS_TXIFLSEL_SET(regs->base.uartifls, TXFIFO_IRQ_TRIGGER_LEVEL);
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regs->base.uartifls =
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PL011_UARTIFLS_RXIFLSEL_SET(regs->base.uartifls, RXFIFO_IRQ_TRIGGER_LEVEL);
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regs->base.uartlcr_h |= PL011_UARTLCR_H_FEN;
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arm_pl011_disable_irq(®s->base, PL011_UARTI_MASK);
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sc = rtems_interrupt_handler_install(
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context->irq,
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"UART",
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RTEMS_INTERRUPT_SHARED,
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arm_pl011_irq_handler,
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context
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);
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if (sc != RTEMS_SUCCESSFUL) {
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return false;
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}
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/* Clear all interrupts */
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arm_pl011_clear_irq(®s->base, PL011_UARTI_MASK);
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arm_pl011_enable_irq(®s->base, PL011_UARTI_RTI | PL011_UARTI_RXI);
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return RTEMS_SUCCESSFUL;
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}
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#endif
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int arm_pl011_compute_baudrate_params(
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uint32_t *ibrd,
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uint32_t *fbrd,
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const uint32_t baudrate,
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const uint32_t clock,
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const unsigned short max_error
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)
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{
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uint16_t scalar;
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uint32_t computed_bauddiv, computed_baudrate, baud_error;
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uint64_t scaled_bauddiv;
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unsigned short round_off, percent_error;
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/*
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* The integer baudrate divisor, i.e. (clock / (baudrate * 16)), value
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* should lie on [1, 2^16 - 1]. To ensure this, clock and baudrate have to
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* be validated.
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*/
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*ibrd = clock / 16 / baudrate;
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if (*ibrd < 1 || *ibrd > PL011_UARTIBRD_BAUD_DIVINT_MASK) {
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return 2;
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}
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/* Find the fractional part */
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scalar = 1 << (PL011_UARTFBRD_BAUD_DIVFRAC_WIDTH + 1);
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scaled_bauddiv =
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((uint64_t) clock * scalar) / 16 / baudrate;
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round_off = scaled_bauddiv & 0x1;
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*fbrd =
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((scaled_bauddiv >> 1) & PL011_UARTFBRD_BAUD_DIVFRAC_MASK) + round_off;
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/* Calculate the baudrate and check if the error is too large */
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computed_bauddiv =
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(*ibrd << PL011_UARTFBRD_BAUD_DIVFRAC_WIDTH) | *fbrd;
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computed_baudrate =
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((uint64_t) clock << PL011_UARTFBRD_BAUD_DIVFRAC_WIDTH)
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/ 16 / computed_bauddiv;
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baud_error = computed_baudrate - baudrate;
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if (baudrate > computed_baudrate) {
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baud_error = baudrate - computed_baudrate;
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}
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percent_error = (baud_error * 100) / baudrate;
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if (percent_error >= max_error) {
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return 1;
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}
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return 0;
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}
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static uint32_t arm_pl011_set_lcrh(const struct termios *term)
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{
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/* enable FIFO */
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uint32_t lcrh = PL011_UARTLCR_H_FEN;
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/* Mode: parity */
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if ((term->c_cflag & PARENB) != 0) {
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lcrh |= PL011_UARTLCR_H_PEN;
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if ((term->c_cflag & PARODD) == 0) {
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lcrh |= PL011_UARTLCR_H_EPS;
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}
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}
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/* Mode: character size */
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switch (term->c_cflag & CSIZE) {
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case CS5:
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lcrh |= PL011_UARTLCR_H_WLEN_SET(lcrh, PL011_UARTLCR_H_WLEN_5);
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break;
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case CS6:
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lcrh |= PL011_UARTLCR_H_WLEN_SET(lcrh, PL011_UARTLCR_H_WLEN_6);
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break;
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case CS7:
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lcrh |= PL011_UARTLCR_H_WLEN_SET(lcrh, PL011_UARTLCR_H_WLEN_7);
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break;
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case CS8:
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default:
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lcrh |= PL011_UARTLCR_H_WLEN_SET(lcrh, PL011_UARTLCR_H_WLEN_8);
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}
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/* Mode: stop bits */
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if ((term->c_cflag & CSTOPB) != 0) {
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/* 2 stop bits */
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lcrh |= PL011_UARTLCR_H_STP2;
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}
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return lcrh;
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}
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static uint32_t arm_pl011_set_cr(const struct termios *term, volatile pl011_base *regs)
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{
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uint32_t cr = regs->uartcr;
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/*
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* Control: Configure flow control
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* NOTE: Flow control is untested
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*/
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cr &= ~(PL011_UARTCR_CTSEN | PL011_UARTCR_RTSEN);
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if ((term->c_cflag & CCTS_OFLOW) != 0) {
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cr |= PL011_UARTCR_CTSEN;
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}
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if ((term->c_cflag & CRTS_IFLOW) != 0) {
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cr |= PL011_UARTCR_RTSEN;
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}
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/* Control: Configure receiver */
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if ((term->c_cflag & CREAD) != 0) {
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cr |= PL011_UARTCR_RXE;
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}
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/* Control: Re-enable UART */
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cr |= PL011_UARTCR_UARTEN | PL011_UARTCR_TXE;
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return cr;
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}
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static bool arm_pl011_set_attributes(
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rtems_termios_device_context *base,
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const struct termios *term
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)
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{
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uint32_t ibrd, fbrd, lcrh, baud, cr;
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int err;
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arm_pl011_context *context = (arm_pl011_context *) base;
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volatile arm_pl011_uart *regs = arm_pl011_get_regs(base);
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/* Determine baudrate parameters */
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baud = rtems_termios_number_to_baud(term->c_ospeed);
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if (baud == B0) {
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return false;
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}
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err = arm_pl011_compute_baudrate_params(&ibrd,&fbrd,baud,context->clock,3);
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if (err != 0) {
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return false;
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}
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lcrh = arm_pl011_set_lcrh(term);
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/* Disable all interrupts */
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arm_pl011_disable_irq(®s->base, PL011_UARTI_MASK);
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/*
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* Wait for any data in the TXFIFO to be sent then wait while the
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* transmiter is active.
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*/
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while (
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(regs->base.uartfr & PL011_UARTFR_TXFE) == 0 ||
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(regs->base.uartfr & PL011_UARTFR_BUSY) != 0
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) {
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/* Wait */
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}
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regs->base.uartcr = PL011_UARTCR_UARTEN;
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/* Set the baudrate */
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regs->base.uartibrd = ibrd;
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regs->base.uartfbrd = fbrd;
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/*
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* Commit mode configurations
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* NOTE:
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* This has to happen after IBRD and FBRD as writing to LCRH is
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* required to trigger the baudrate update.
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*/
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regs->base.uartlcr_h = lcrh;
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/* Control: Disable UART */
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regs->base.uartcr &=
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~(PL011_UARTCR_UARTEN | PL011_UARTCR_RXE | PL011_UARTCR_TXE);
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cr = arm_pl011_set_cr(term, ®s->base);
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arm_pl011_flush_fifos(context);
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/* Commit changes to control register */
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regs->base.uartcr = cr;
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#ifdef BSP_CONSOLE_USE_INTERRUPTS
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/* Clear all interrupts */
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arm_pl011_clear_irq(®s->base, PL011_UARTI_MASK);
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/* Re-enable RX interrupts */
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if ((term->c_cflag & CREAD) != 0) {
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arm_pl011_enable_irq(®s->base, PL011_UARTI_RTI | PL011_UARTI_RXI);
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}
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/*
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* UART is freshly enabled, TXFIFO is empty, and interrupt will be enabled,
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* so the next transmission will required software-trigger interrupt.
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*/
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context->needs_sw_triggered_tx_irq = true;
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#endif
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return true;
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}
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static bool arm_pl011_first_open(
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struct rtems_termios_tty *tty,
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rtems_termios_device_context *base,
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struct termios *term,
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rtems_libio_open_close_args_t *args
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)
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{
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arm_pl011_context *context = (arm_pl011_context *) base;
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#ifdef BSP_CONSOLE_USE_INTERRUPTS
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rtems_status_code sc;
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context->tty = tty;
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#endif
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if (rtems_termios_set_initial_baud(tty, context->initial_baud) != 0) {
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return false;
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}
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if (!arm_pl011_set_attributes(base, term)) {
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return false;
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}
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#ifdef BSP_CONSOLE_USE_INTERRUPTS
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sc = arm_pl011_first_open_irq(base, context);
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if (sc != RTEMS_SUCCESSFUL) {
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return false;
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}
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#endif
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return true;
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}
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#ifdef BSP_CONSOLE_USE_INTERRUPTS
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static void arm_pl011_last_close(
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rtems_termios_tty *tty,
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rtems_termios_device_context *base,
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rtems_libio_open_close_args_t *args
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)
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{
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const arm_pl011_context *context = (void *) base;
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(void) rtems_interrupt_handler_remove(
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context->irq,
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arm_pl011_irq_handler,
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tty
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);
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}
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#endif
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int arm_pl011_read_polled(rtems_termios_device_context *base)
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{
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volatile arm_pl011_uart *regs = arm_pl011_get_regs(base);
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if (arm_pl011_is_rxfifo_empty(®s->base)) {
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return -1;
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} else {
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return arm_pl011_read_char(®s->base);
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}
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}
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void arm_pl011_write_polled(rtems_termios_device_context *base, char c)
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{
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volatile arm_pl011_uart *regs = arm_pl011_get_regs(base);
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/* Wait until TXFIFO has space */
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while (arm_pl011_is_txfifo_full(®s->base)) {
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/* Wait */
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}
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arm_pl011_write_char(®s->base, c);
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}
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#ifdef BSP_CONSOLE_USE_INTERRUPTS
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static void arm_pl011_write_support_interrupt(
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rtems_termios_device_context *base,
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const char *buffer,
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size_t buffer_len
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)
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{
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arm_pl011_context *context = (arm_pl011_context *) base;
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volatile arm_pl011_uart *regs = arm_pl011_get_regs(base);
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size_t i = 0;
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if (buffer_len > 0) {
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arm_pl011_enable_irq(®s->base, PL011_UARTI_TXI);
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/*
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* When arm_pl011_write_support_interrupt writes the first character,
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* if txfifo is full, it will return directly. This will cause this
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* character to be lost. If txfifo is full, wait for it to be not full.
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*/
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while (arm_pl011_is_txfifo_full(®s->base)) {
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/* wait for txfifo not full */
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}
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while (!arm_pl011_is_txfifo_full(®s->base) && i < buffer_len) {
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arm_pl011_write_char(®s->base, buffer[i]);
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i++;
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}
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context->tx_queued_chars = i;
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if (context->needs_sw_triggered_tx_irq) {
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/*
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* The first write may not trigger the TX interrupt due to insufficient
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* characters being written. Call rtems_termios_dequeue_characters() to
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* continue writing.
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*/
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(void) rtems_termios_dequeue_characters(context->tty,
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context->tx_queued_chars);
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}
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} else {
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/*
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* Termios will set n to zero to indicate that the transmitter is now
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* inactive. The output buffer is empty in this case. The driver may
|
|
* disable the transmit interrupts now.
|
|
*/
|
|
arm_pl011_disable_irq(®s->base, PL011_UARTI_TXI);
|
|
}
|
|
}
|
|
#else
|
|
static void arm_pl011_write_support_polled(
|
|
rtems_termios_device_context *base,
|
|
const char *s,
|
|
size_t n
|
|
)
|
|
{
|
|
size_t i;
|
|
|
|
for (i = 0; i < n; ++i) {
|
|
arm_pl011_write_polled(base, s[i]);
|
|
}
|
|
}
|
|
#endif
|
|
|
|
static void arm_pl011_write_buffer(
|
|
rtems_termios_device_context *base,
|
|
const char *buffer,
|
|
size_t n
|
|
)
|
|
{
|
|
#ifdef BSP_CONSOLE_USE_INTERRUPTS
|
|
arm_pl011_write_support_interrupt(base, buffer, n);
|
|
#else
|
|
arm_pl011_write_support_polled(base, buffer, n);
|
|
#endif
|
|
}
|
|
|
|
const rtems_termios_device_handler arm_pl011_fns = {
|
|
.first_open = arm_pl011_first_open,
|
|
.write = arm_pl011_write_buffer,
|
|
.set_attributes = arm_pl011_set_attributes,
|
|
.ioctl = NULL,
|
|
#ifdef BSP_CONSOLE_USE_INTERRUPTS
|
|
.last_close = arm_pl011_last_close,
|
|
.poll_read = NULL,
|
|
.mode = TERMIOS_IRQ_DRIVEN,
|
|
#else
|
|
.last_close = NULL,
|
|
.poll_read = arm_pl011_read_polled,
|
|
.mode = TERMIOS_POLLED,
|
|
#endif
|
|
}; |