forked from Imagelibrary/rtems
838 lines
17 KiB
C
838 lines
17 KiB
C
/**
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* @file
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*
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* @brief Definitions for ATmega325 and ATmega325P
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*
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* This file should only be included from <avr/io.h>, never directly.
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*/
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/* Copyright (c) 2004, 2005, 2006, 2007 Eric B. Weddington
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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* Neither the name of the copyright holders nor the names of
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contributors may be used to endorse or promote products derived
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from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE. */
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/* avr/iom325.h - definitions for ATmega325 and ATmega325P. */
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#ifndef _AVR_IOM325_H_
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#define _AVR_IOM325_H_ 1
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/* This file should only be included from <avr/io.h>, never directly. */
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#ifndef _AVR_IO_H_
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# error "Include <avr/io.h> instead of this file."
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#endif
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#ifndef _AVR_IOXXX_H_
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# define _AVR_IOXXX_H_ "iom325.h"
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#else
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# error "Attempt to include more than one <avr/ioXXX.h> file."
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#endif
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/**
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* @defgroup AvrDef_iom325 ATmega325 and ATmega325P Definitions
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*
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* @ingroup avr
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*
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*/
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/**@{**/
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/* Registers and associated bit numbers */
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#define PINA _SFR_IO8(0x00)
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#define PINA7 7
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#define PINA6 6
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#define PINA5 5
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#define PINA4 4
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#define PINA3 3
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#define PINA2 2
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#define PINA1 1
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#define PINA0 0
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#define DDRA _SFR_IO8(0x01)
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#define DDA7 7
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#define DDA6 6
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#define DDA5 5
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#define DDA4 4
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#define DDA3 3
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#define DDA2 2
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#define DDA1 1
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#define DDA0 0
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#define PORTA _SFR_IO8(0x02)
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#define PA7 7
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#define PA6 6
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#define PA5 5
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#define PA4 4
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#define PA3 3
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#define PA2 2
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#define PA1 1
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#define PA0 0
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#define PINB _SFR_IO8(0x03)
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#define PINB7 7
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#define PINB6 6
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#define PINB5 5
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#define PINB4 4
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#define PINB3 3
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#define PINB2 2
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#define PINB1 1
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#define PINB0 0
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#define DDRB _SFR_IO8(0x04)
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#define DDB7 7
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#define DDB6 6
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#define DDB5 5
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#define DDB4 4
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#define DDB3 3
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#define DDB2 2
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#define DDB1 1
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#define DDB0 0
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#define PORTB _SFR_IO8(0x05)
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#define PB7 7
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#define PB6 6
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#define PB5 5
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#define PB4 4
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#define PB3 3
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#define PB2 2
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#define PB1 1
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#define PB0 0
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#define PINC _SFR_IO8(0x06)
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#define PINC7 7
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#define PINC6 6
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#define PINC5 5
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#define PINC4 4
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#define PINC3 3
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#define PINC2 2
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#define PINC1 1
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#define PINC0 0
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#define DDRC _SFR_IO8(0x07)
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#define DDC7 7
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#define DDC6 6
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#define DDC5 5
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#define DDC4 4
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#define DDC3 3
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#define DDC2 2
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#define DDC1 1
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#define DDC0 0
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#define PORTC _SFR_IO8(0x08)
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#define PC7 7
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#define PC6 6
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#define PC5 5
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#define PC4 4
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#define PC3 3
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#define PC2 2
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#define PC1 1
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#define PC0 0
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#define PIND _SFR_IO8(0x09)
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#define PIND7 7
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#define PIND6 6
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#define PIND5 5
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#define PIND4 4
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#define PIND3 3
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#define PIND2 2
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#define PIND1 1
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#define PIND0 0
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#define DDRD _SFR_IO8(0x0A)
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#define DDD7 7
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#define DDD6 6
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#define DDD5 5
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#define DDD4 4
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#define DDD3 3
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#define DDD2 2
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#define DDD1 1
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#define DDD0 0
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#define PORTD _SFR_IO8(0x0B)
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#define PD7 7
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#define PD6 6
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#define PD5 5
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#define PD4 4
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#define PD3 3
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#define PD2 2
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#define PD1 1
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#define PD0 0
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#define PINE _SFR_IO8(0x0C)
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#define PINE7 7
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#define PINE6 6
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#define PINE5 5
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#define PINE4 4
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#define PINE3 3
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#define PINE2 2
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#define PINE1 1
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#define PINE0 0
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#define DDRE _SFR_IO8(0x0D)
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#define DDE7 7
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#define DDE6 6
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#define DDE5 5
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#define DDE4 4
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#define DDE3 3
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#define DDE2 2
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#define DDE1 1
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#define DDE0 0
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#define PORTE _SFR_IO8(0x0E)
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#define PE7 7
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#define PE6 6
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#define PE5 5
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#define PE4 4
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#define PE3 3
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#define PE2 2
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#define PE1 1
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#define PE0 0
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#define PINF _SFR_IO8(0x0F)
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#define PINF7 7
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#define PINF6 6
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#define PINF5 5
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#define PINF4 4
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#define PINF3 3
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#define PINF2 2
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#define PINF1 1
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#define PINF0 0
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#define DDRF _SFR_IO8(0x10)
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#define DDF7 7
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#define DDF6 6
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#define DDF5 5
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#define DDF4 4
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#define DDF3 3
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#define DDF2 2
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#define DDF1 1
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#define DDF0 0
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#define PORTF _SFR_IO8(0x11)
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#define PF7 7
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#define PF6 6
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#define PF5 5
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#define PF4 4
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#define PF3 3
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#define PF2 2
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#define PF1 1
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#define PF0 0
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#define PING _SFR_IO8(0x12)
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#define PING5 5
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#define PING4 4
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#define PING3 3
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#define PING2 2
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#define PING1 1
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#define PING0 0
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#define DDRG _SFR_IO8(0x13)
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#define DDG4 4
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#define DDG3 3
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#define DDG2 2
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#define DDG1 1
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#define DDG0 0
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#define PORTG _SFR_IO8(0x14)
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#define PG4 4
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#define PG3 3
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#define PG2 2
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#define PG1 1
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#define PG0 0
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#define TIFR0 _SFR_IO8(0x15)
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#define TOV0 0
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#define OCF0A 1
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#define TIFR1 _SFR_IO8(0x16)
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#define TOV1 0
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#define OCF1A 1
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#define OCF1B 2
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#define ICF1 5
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#define TIFR2 _SFR_IO8(0x17)
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#define TOV2 0
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#define OCF2A 1
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/* Reserved [0x18..0x1B] */
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#define EIFR _SFR_IO8(0x1C)
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#define INTF0 0
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#define PCIF0 4
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#define PCIF1 5
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#define EIMSK _SFR_IO8(0x1D)
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#define INT0 0
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#define PCIE0 4
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#define PCIE1 5
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#define GPIOR0 _SFR_IO8(0x1E)
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#define EECR _SFR_IO8(0x1F)
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#define EERE 0
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#define EEWE 1
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#define EEMWE 2
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#define EERIE 3
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#define EEDR _SFR_IO8(0X20)
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/* Combine EEARL and EEARH */
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#define EEAR _SFR_IO16(0x21)
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#define EEARL _SFR_IO8(0x21)
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#define EEARH _SFR_IO8(0X22)
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/* 6-char sequence denoting where to find the EEPROM registers in memory space.
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Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
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subroutines.
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First two letters: EECR address.
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Second two letters: EEDR address.
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Last two letters: EEAR address. */
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#define __EEPROM_REG_LOCATIONS__ 1F2021
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#define GTCCR _SFR_IO8(0x23)
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#define PSR10 0
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#define PSR2 1
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#define TSM 7
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#define TCCR0A _SFR_IO8(0x24)
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#define CS00 0
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#define CS01 1
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#define CS02 2
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#define WGM01 3
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#define COM0A0 4
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#define COM0A1 5
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#define WGM00 6
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#define FOC0A 7
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/* Reserved [0x25] */
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#define TCNT0 _SFR_IO8(0X26)
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#define OCR0A _SFR_IO8(0X27)
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/* Reserved [0x28..0x29] */
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#define GPIOR1 _SFR_IO8(0x2A)
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#define GPIOR2 _SFR_IO8(0x2B)
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#define SPCR _SFR_IO8(0x2C)
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#define SPR0 0
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#define SPR1 1
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#define CPHA 2
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#define CPOL 3
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#define MSTR 4
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#define DORD 5
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#define SPE 6
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#define SPIE 7
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#define SPSR _SFR_IO8(0x2D)
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#define SPI2X 0
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#define WCOL 6
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#define SPIF 7
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#define SPDR _SFR_IO8(0X2E)
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/* Reserved [0x2F] */
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#define ACSR _SFR_IO8(0x30)
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#define ACIS0 0
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#define ACIS1 1
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#define ACIC 2
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#define ACIE 3
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#define ACI 4
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#define ACO 5
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#define ACBG 6
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#define ACD 7
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#define OCDR _SFR_IO8(0x31)
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#define OCDR0 0
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#define OCDR1 1
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#define OCDR2 2
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#define OCDR3 3
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#define OCDR4 4
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#define OCDR5 5
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#define OCDR6 6
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#define OCDR7 7
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#define IDRD 7
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/* Reserved [0x32] */
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#define SMCR _SFR_IO8(0x33)
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#define SE 0
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#define SM0 1
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#define SM1 2
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#define SM2 3
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#define MCUSR _SFR_IO8(0x34)
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#define PORF 0
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#define EXTRF 1
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#define BORF 2
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#define WDRF 3
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#define JTRF 4
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#define MCUCR _SFR_IO8(0X35)
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#define IVCE 0
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#define IVSEL 1
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#define PUD 4
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#if defined(__AVR_ATmega325P__)
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#define BODSE 5
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#define BODS 6
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#endif
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#define JTD 7
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/* Reserved [0x36] */
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#define SPMCSR _SFR_IO8(0x37)
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#define SPMEN 0
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#define PGERS 1
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#define PGWRT 2
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#define BLBSET 3
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#define RWWSRE 4
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#define RWWSB 6
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#define SPMIE 7
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/* Reserved [0x38..0x3C] */
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/* SP [0x3D..0x3E] */
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/* SREG [0x3F] */
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#define WDTCR _SFR_MEM8(0x60)
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#define WDP0 0
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#define WDP1 1
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#define WDP2 2
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#define WDE 3
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#define WDCE 4
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#define CLKPR _SFR_MEM8(0x61)
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#define CLKPS0 0
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#define CLKPS1 1
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#define CLKPS2 2
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#define CLKPS3 3
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#define CLKPCE 7
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/* Reserved [0x62..0x63] */
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#define PRR _SFR_MEM8(0x64)
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#define PRADC 0
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#define PRUSART0 1
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#define PRSPI 2
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#define PRTIM1 3
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/* Reserved [0x65] */
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#define OSCCAL _SFR_MEM8(0x66)
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/* Reserved [0x67..0x68] */
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#define EICRA _SFR_MEM8(0x69)
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#define ISC00 0
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#define ISC01 1
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/* Reserved [0x6A] */
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#define PCMSK0 _SFR_MEM8(0x6B)
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#define PCINT0 0
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#define PCINT1 1
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#define PCINT2 2
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#define PCINT3 3
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#define PCINT4 4
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#define PCINT5 5
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#define PCINT6 6
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#define PCINT7 7
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#define PCMSK1 _SFR_MEM8(0x6C)
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#define PCINT8 0
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#define PCINT9 1
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#define PCINT10 2
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#define PCINT11 3
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#define PCINT12 4
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#define PCINT13 5
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#define PCINT14 6
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#define PCINT15 7
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/* Reserved [0x6D] */
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#define TIMSK0 _SFR_MEM8(0x6E)
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#define TOIE0 0
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#define OCIE0A 1
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#define TIMSK1 _SFR_MEM8(0x6F)
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#define TOIE1 0
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#define OCIE1A 1
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#define OCIE1B 2
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#define ICIE1 5
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#define TIMSK2 _SFR_MEM8(0x70)
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#define TOIE2 0
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#define OCIE2A 1
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/* Reserved [0x71..0x77] */
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/* Combine ADCL and ADCH */
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#ifndef __ASSEMBLER__
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#define ADC _SFR_MEM16(0x78)
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#endif
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#define ADCW _SFR_MEM16(0x78)
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#define ADCL _SFR_MEM8(0x78)
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#define ADCH _SFR_MEM8(0x79)
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#define ADCSRA _SFR_MEM8(0x7A)
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#define ADPS0 0
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#define ADPS1 1
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#define ADPS2 2
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#define ADIE 3
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#define ADIF 4
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#define ADATE 5
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#define ADSC 6
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#define ADEN 7
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#define ADCSRB _SFR_MEM8(0x7B)
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#define ADTS0 0
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#define ADTS1 1
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#define ADTS2 2
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#define ACME 6
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#define ADMUX _SFR_MEM8(0x7C)
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#define MUX0 0
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#define MUX1 1
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#define MUX2 2
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#define MUX3 3
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#define MUX4 4
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#define ADLAR 5
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#define REFS0 6
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#define REFS1 7
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/* Reserved [0x7D] */
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#define DIDR0 _SFR_MEM8(0x7E)
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#define ADC0D 0
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#define ADC1D 1
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#define ADC2D 2
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#define ADC3D 3
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#define ADC4D 4
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#define ADC5D 5
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#define ADC6D 6
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#define ADC7D 7
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#define DIDR1 _SFR_MEM8(0x7F)
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#define AIN0D 0
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#define AIN1D 1
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#define TCCR1A _SFR_MEM8(0X80)
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#define WGM10 0
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#define WGM11 1
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#define COM1B0 4
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#define COM1B1 5
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#define COM1A0 6
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#define COM1A1 7
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#define TCCR1B _SFR_MEM8(0X81)
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#define CS10 0
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#define CS11 1
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#define CS12 2
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#define WGM12 3
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#define WGM13 4
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#define ICES1 6
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#define ICNC1 7
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#define TCCR1C _SFR_MEM8(0x82)
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#define FOC1B 6
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#define FOC1A 7
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/* Reserved [0x83] */
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/* Combine TCNT1L and TCNT1H */
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#define TCNT1 _SFR_MEM16(0x84)
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#define TCNT1L _SFR_MEM8(0x84)
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#define TCNT1H _SFR_MEM8(0x85)
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/* Combine ICR1L and ICR1H */
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#define ICR1 _SFR_MEM16(0x86)
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#define ICR1L _SFR_MEM8(0x86)
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#define ICR1H _SFR_MEM8(0x87)
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/* Combine OCR1AL and OCR1AH */
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#define OCR1A _SFR_MEM16(0x88)
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#define OCR1AL _SFR_MEM8(0x88)
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#define OCR1AH _SFR_MEM8(0x89)
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/* Combine OCR1BL and OCR1BH */
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#define OCR1B _SFR_MEM16(0x8A)
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#define OCR1BL _SFR_MEM8(0x8A)
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#define OCR1BH _SFR_MEM8(0x8B)
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/* Reserved [0x8C..0xAF] */
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#define TCCR2A _SFR_MEM8(0xB0)
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#define CS20 0
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#define CS21 1
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#define CS22 2
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#define WGM21 3
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#define COM2A0 4
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#define COM2A1 5
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#define WGM20 6
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#define FOC2A 7
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/* Reserved [0xB1] */
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#define TCNT2 _SFR_MEM8(0xB2)
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#define OCR2A _SFR_MEM8(0xB3)
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/* Reserved [0xB4..0xB5] */
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#define ASSR _SFR_MEM8(0xB6)
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#define TCR2UB 0
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#define OCR2UB 1
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#define TCN2UB 2
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#define AS2 3
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#define EXCLK 4
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/* Reserved [0xB7] */
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#define USICR _SFR_MEM8(0xB8)
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#define USITC 0
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#define USICLK 1
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#define USICS0 2
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#define USICS1 3
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#define USIWM0 4
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#define USIWM1 5
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#define USIOIE 6
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#define USISIE 7
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#define USISR _SFR_MEM8(0xB9)
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#define USICNT0 0
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#define USICNT1 1
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#define USICNT2 2
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#define USICNT3 3
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#define USIDC 4
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#define USIPF 5
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#define USIOIF 6
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#define USISIF 7
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#define USIDR _SFR_MEM8(0xBA)
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/* Reserved [0xBB..0xBF] */
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#define UCSR0A _SFR_MEM8(0xC0)
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#define MPCM0 0
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#define U2X0 1
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#define UPE0 2
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#define DOR0 3
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#define FE0 4
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#define UDRE0 5
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#define TXC0 6
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#define RXC0 7
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#define UCSR0B _SFR_MEM8(0XC1)
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#define TXB80 0
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#define RXB80 1
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#define UCSZ02 2
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#define TXEN0 3
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#define RXEN0 4
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#define UDRIE0 5
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#define TXCIE0 6
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#define RXCIE0 7
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#define UCSR0C _SFR_MEM8(0xC2)
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#define UCPOL0 0
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#define UCSZ00 1
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#define UCSZ01 2
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#define USBS0 3
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#define UPM00 4
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#define UPM01 5
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#define UMSEL0 6
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|
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/* Reserved [0xC3] */
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|
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/* Combine UBRR0L and UBRR0H */
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#define UBRR0 _SFR_MEM16(0xC4)
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#define UBRR0L _SFR_MEM8(0xC4)
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#define UBRR0H _SFR_MEM8(0xC5)
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#define UDR0 _SFR_MEM8(0XC6)
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/* Reserved [0xC7..0xFF] */
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/* Interrupt vectors */
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/* Vector 0 is the reset vector */
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/* External Interrupt Request 0 */
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#define INT0_vect _VECTOR(1)
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#define SIG_INTERRUPT0 _VECTOR(1)
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|
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/* Pin Change Interrupt Request 0 */
|
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#define PCINT0_vect _VECTOR(2)
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#define SIG_PIN_CHANGE0 _VECTOR(2)
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/* Pin Change Interrupt Request 1 */
|
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#define PCINT1_vect _VECTOR(3)
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#define SIG_PIN_CHANGE1 _VECTOR(3)
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|
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/* Timer/Counter2 Compare Match */
|
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#define TIMER2_COMP_vect _VECTOR(4)
|
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#define SIG_OUTPUT_COMPARE2 _VECTOR(4)
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|
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/* Timer/Counter2 Overflow */
|
|
#define TIMER2_OVF_vect _VECTOR(5)
|
|
#define SIG_OVERFLOW2 _VECTOR(5)
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|
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/* Timer/Counter1 Capture Event */
|
|
#define TIMER1_CAPT_vect _VECTOR(6)
|
|
#define SIG_INPUT_CAPTURE1 _VECTOR(6)
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|
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/* Timer/Counter1 Compare Match A */
|
|
#define TIMER1_COMPA_vect _VECTOR(7)
|
|
#define SIG_OUTPUT_COMPARE1A _VECTOR(7)
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|
|
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/* Timer/Counter Compare Match B */
|
|
#define TIMER1_COMPB_vect _VECTOR(8)
|
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#define SIG_OUTPUT_COMPARE1B _VECTOR(8)
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|
|
|
/* Timer/Counter1 Overflow */
|
|
#define TIMER1_OVF_vect _VECTOR(9)
|
|
#define SIG_OVERFLOW1 _VECTOR(9)
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|
|
|
/* Timer/Counter0 Compare Match */
|
|
#define TIMER0_COMP_vect _VECTOR(10)
|
|
#define SIG_OUTPUT_COMPARE0 _VECTOR(10)
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|
|
|
/* Timer/Counter0 Overflow */
|
|
#define TIMER0_OVF_vect _VECTOR(11)
|
|
#define SIG_OVERFLOW0 _VECTOR(11)
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|
|
|
/* SPI Serial Transfer Complete */
|
|
#define SPI_STC_vect _VECTOR(12)
|
|
#define SIG_SPI _VECTOR(12)
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|
|
|
/* USART0, Rx Complete */
|
|
#define USART0_RX_vect _VECTOR(13)
|
|
#define SIG_UART_RECV _VECTOR(13)
|
|
|
|
/* USART0 Data register Empty */
|
|
#define USART0_UDRE_vect _VECTOR(14)
|
|
#define SIG_UART_DATA _VECTOR(14)
|
|
|
|
/* USART0, Tx Complete */
|
|
#define USART0_TX_vect _VECTOR(15)
|
|
#define SIG_UART_TRANS _VECTOR(15)
|
|
|
|
/* USI Start Condition */
|
|
#define USI_START_vect _VECTOR(16)
|
|
#define SIG_USI_START _VECTOR(16)
|
|
|
|
/* USI Overflow */
|
|
#define USI_OVERFLOW_vect _VECTOR(17)
|
|
#define SIG_USI_OVERFLOW _VECTOR(17)
|
|
|
|
/* Analog Comparator */
|
|
#define ANALOG_COMP_vect _VECTOR(18)
|
|
#define SIG_COMPARATOR _VECTOR(18)
|
|
|
|
/* ADC Conversion Complete */
|
|
#define ADC_vect _VECTOR(19)
|
|
#define SIG_ADC _VECTOR(19)
|
|
|
|
/* EEPROM Ready */
|
|
#define EE_READY_vect _VECTOR(20)
|
|
#define SIG_EEPROM_READY _VECTOR(20)
|
|
|
|
/* Store Program Memory Read */
|
|
#define SPM_READY_vect _VECTOR(21)
|
|
#define SIG_SPM_READY _VECTOR(21)
|
|
|
|
/* Vector 22 is Reserved */
|
|
|
|
#define _VECTORS_SIZE 92
|
|
|
|
|
|
/* Constants */
|
|
#define SPM_PAGESIZE 128
|
|
#define RAMEND 0x8FF
|
|
#define XRAMEND RAMEND
|
|
#define E2END 0x3FF
|
|
#define E2PAGESIZE 4
|
|
#define FLASHEND 0x7FFF
|
|
|
|
|
|
/* Fuses */
|
|
|
|
#define FUSE_MEMORY_SIZE 3
|
|
|
|
/* Low Fuse Byte */
|
|
#define FUSE_CKSEL0 (unsigned char)~_BV(0)
|
|
#define FUSE_CKSEL1 (unsigned char)~_BV(1)
|
|
#define FUSE_CKSEL2 (unsigned char)~_BV(2)
|
|
#define FUSE_CKSEL3 (unsigned char)~_BV(3)
|
|
#define FUSE_SUT0 (unsigned char)~_BV(4)
|
|
#define FUSE_SUT1 (unsigned char)~_BV(5)
|
|
#define FUSE_CKOUT (unsigned char)~_BV(6)
|
|
#define FUSE_CKDIV8 (unsigned char)~_BV(7)
|
|
#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
|
|
|
|
/* High Fuse Byte */
|
|
#define FUSE_BOOTRST (unsigned char)~_BV(0)
|
|
#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)
|
|
#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)
|
|
#define FUSE_EESAVE (unsigned char)~_BV(3)
|
|
#define FUSE_WDTON (unsigned char)~_BV(4)
|
|
#define FUSE_SPIEN (unsigned char)~_BV(5)
|
|
#define FUSE_JTAGEN (unsigned char)~_BV(6)
|
|
#define FUSE_OCDEN (unsigned char)~_BV(7)
|
|
#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
|
|
|
|
/* Extended Fuse Byte */
|
|
#define FUSE_RSTDISBL (unsigned char)~_BV(0)
|
|
#define FUSE_BODLEVEL0 (unsigned char)~_BV(1)
|
|
#define FUSE_BODLEVEL1 (unsigned char)~_BV(2)
|
|
#define EFUSE_DEFAULT (0xFF)
|
|
|
|
|
|
/* Lock Bits */
|
|
#define __LOCK_BITS_EXIST
|
|
#define __BOOT_LOCK_BITS_0_EXIST
|
|
#define __BOOT_LOCK_BITS_1_EXIST
|
|
|
|
|
|
/* Signature */
|
|
#define SIGNATURE_0 0x1E
|
|
#define SIGNATURE_1 0x95
|
|
#define SIGNATURE_2 0x05
|
|
|
|
/** @} */
|
|
|
|
#endif /* _AVR_IOM325_H_ */
|