forked from Imagelibrary/rtems
f9fbb3336f
The refactoring of pci_dev_create() was incorrect since the code relied on different defines before including pci/cfg.h. This reverts back to the original code having two pci_dev_create() one in auto and one in read library. confdefs.h selectes between the two libraries so both there is no link conflict. Updates #3029
355 lines
8.6 KiB
C
355 lines
8.6 KiB
C
/* Read current PCI configuration that bootloader or BIOS has already setup
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* and initialize the PCI structures.
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*
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* COPYRIGHT (c) 2010 Cobham Gaisler AB.
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#include <rtems.h>
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#include <stdlib.h>
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#include <rtems/bspIo.h>
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#include <pci/cfg.h>
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#include <pci/access.h>
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#include "pci_internal.h"
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/* PCI Library
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* (For debugging it might be good to use other functions or the driver's
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* directly)
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*/
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#define PCI_CFG_R8(dev, args...) pci_cfg_r8(dev, args)
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#define PCI_CFG_R16(dev, args...) pci_cfg_r16(dev, args)
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#define PCI_CFG_R32(dev, args...) pci_cfg_r32(dev, args)
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#define PCI_CFG_W8(dev, args...) pci_cfg_w8(dev, args)
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#define PCI_CFG_W16(dev, args...) pci_cfg_w16(dev, args)
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#define PCI_CFG_W32(dev, args...) pci_cfg_w32(dev, args)
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#ifdef DEBUG
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#define DBG(args...) printk(args)
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#else
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#define DBG(args...)
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#endif
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/* The Host Bridge bus is initialized here */
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extern struct pci_bus pci_hb;
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static struct pci_dev *pci_dev_create(int isbus)
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{
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void *ptr;
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int size;
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if (isbus)
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size = sizeof(struct pci_bus);
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else
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size = sizeof(struct pci_dev);
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ptr = calloc(1, size);
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if (!ptr)
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rtems_fatal_error_occurred(RTEMS_NO_MEMORY);
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return ptr;
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}
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/* Check if address is accessible from host */
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static int pci_read_addressable(struct pci_dev *dev, struct pci_res *res)
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{
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struct pci_bus *bus = dev->bus;
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int type = res->flags & PCI_RES_TYPE_MASK;
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struct pci_res *range0, *range1;
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if (type == PCI_BUS_IO && (bus->flags & PCI_BUS_IO) == 0)
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return 0;
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/* Assume that host bridge can access all */
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if (bus->pri == 0)
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return 1;
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range1 = NULL;
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switch (type) {
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case PCI_RES_IO:
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range0 = &bus->dev.resources[BRIDGE_RES_IO];
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break;
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case PCI_RES_MEM:
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range1 = &bus->dev.resources[BRIDGE_RES_MEM];
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default:
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case PCI_RES_MEMIO:
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range0 = &bus->dev.resources[BRIDGE_RES_MEMIO];
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break;
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}
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if ((res->start >= range0->start) && (res->end <= range0->end)) {
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return pci_read_addressable(&bus->dev, range0);
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} else if (range1 && (res->start >= range1->start) &&
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(res->end <= range1->end)) {
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return pci_read_addressable(&bus->dev, range1);
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}
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return 0;
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}
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static void pci_read_bar(struct pci_dev *dev, int bar)
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{
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uint32_t orig, size, mask;
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struct pci_res *res = &dev->resources[bar];
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pci_dev_t pcidev = dev->busdevfun;
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int ofs;
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#ifdef DEBUG
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char *str;
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#define DBG_SET_STR(str, val) str = (val)
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#else
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#define DBG_SET_STR(str, val)
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#endif
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DBG("Bus: %x, Slot: %x, function: %x, bar%d\n",
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PCI_DEV_EXPAND(pcidev), bar);
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res->bar = bar;
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if (bar == DEV_RES_ROM) {
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if (dev->flags & PCI_DEV_BRIDGE)
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ofs = PCIR_BIOS_1;
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else
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ofs = PCIR_BIOS;
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} else {
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ofs = PCIR_BAR(0) + (bar << 2);
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}
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PCI_CFG_R32(pcidev, ofs, &orig);
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PCI_CFG_W32(pcidev, ofs, 0xffffffff);
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PCI_CFG_R32(pcidev, ofs, &size);
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PCI_CFG_W32(pcidev, ofs, orig);
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if (size == 0 || size == 0xffffffff)
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return;
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if (bar == DEV_RES_ROM) {
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mask = PCIM_BIOS_ADDR_MASK;
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DBG_SET_STR(str, "ROM");
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if (dev->bus->flags & PCI_BUS_MEM)
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res->flags = PCI_RES_MEM;
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else
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res->flags = PCI_RES_MEMIO;
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} else if (((size & 0x1) == 0) && (size & 0x6)) {
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/* unsupported Memory type */
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return;
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} else {
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mask = ~0xf;
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if (size & 0x1) {
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/* I/O */
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mask = ~0x3;
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res->flags = PCI_RES_IO;
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DBG_SET_STR(str, "I/O");
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if (size & 0xffff0000)
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res->flags |= PCI_RES_IO32;
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/* Limit size of I/O space to 256 byte */
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size |= 0xffffff00;
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if ((dev->bus->flags & PCI_BUS_IO) == 0) {
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res->flags |= PCI_RES_FAIL;
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dev->flags |= PCI_DEV_RES_FAIL;
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}
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} else {
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/* Memory */
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if (size & 0x8) {
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/* Prefetchable */
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res->flags = PCI_RES_MEM;
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DBG_SET_STR(str, "MEM");
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} else {
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res->flags = PCI_RES_MEMIO;
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DBG_SET_STR(str, "MEMIO");
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}
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}
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}
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res->start = orig & mask;
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size &= mask;
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res->size = ~size + 1;
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res->boundary = res->size;
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res->end = res->start + res->size;
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DBG("Bus: %x, Slot: %x, function: %x, %s bar%d size: %x\n",
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PCI_DEV_EXPAND(pcidev), str, bar, res->size);
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/* Check if BAR is addressable by host */
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if (pci_read_addressable(dev, res) == 0) {
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/* No matching bridge window contains this BAR */
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res->flags |= PCI_RES_FAIL;
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dev->flags |= PCI_DEV_RES_FAIL;
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}
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}
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static void pci_read_devs(struct pci_bus *bus)
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{
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uint32_t id, tmp;
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uint16_t tmp16;
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uint8_t header;
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int slot, func, fail, i, maxbars, max_sord;
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struct pci_dev *dev, **listptr;
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struct pci_bus *bridge;
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pci_dev_t pcidev;
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struct pci_res *res;
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DBG("Scanning bus %d\n", bus->num);
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max_sord = bus->num;
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listptr = &bus->devs;
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for (slot = 0; slot <= PCI_SLOTMAX; slot++) {
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/* Slot address */
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pcidev = PCI_DEV(bus->num, slot, 0);
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for (func = 0; func <= PCI_FUNCMAX; func++, pcidev++) {
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fail = PCI_CFG_R32(pcidev, PCIR_VENDOR, &id);
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if (fail || id == 0xffffffff || id == 0) {
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/*
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* This slot is empty
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*/
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if (func == 0)
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break;
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else
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continue;
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}
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DBG("Found PCIDEV 0x%x at (bus %x, slot %x, func %x)\n",
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id, bus, slot, func);
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PCI_CFG_R32(pcidev, PCIR_REVID, &tmp);
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tmp >>= 16;
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dev = pci_dev_create(tmp == PCID_PCI2PCI_BRIDGE);
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*listptr = dev;
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listptr = &dev->next;
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dev->busdevfun = pcidev;
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dev->bus = bus;
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PCI_CFG_R16(pcidev, PCIR_VENDOR, &dev->vendor);
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PCI_CFG_R16(pcidev, PCIR_DEVICE, &dev->device);
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PCI_CFG_R32(pcidev, PCIR_REVID, &dev->classrev);
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if (tmp == PCID_PCI2PCI_BRIDGE) {
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DBG("Found PCI-PCI Bridge 0x%x at "
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"(bus %x, slot %x, func %x)\n",
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id, bus, slot, func);
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dev->flags = PCI_DEV_BRIDGE;
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bridge = (struct pci_bus *)dev;
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PCI_CFG_R32(pcidev, PCIR_PRIBUS_1, &tmp);
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bridge->pri = tmp & 0xff;
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bridge->num = (tmp >> 8) & 0xff;
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bridge->sord = (tmp >> 16) & 0xff;
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if (bridge->sord > max_sord)
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max_sord = bridge->sord;
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DBG(" Primary %x, Secondary %x, "
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"Subordinate %x\n",
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bridge->pri, bridge->num, bridge->sord);
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/*** Probe Bridge Spaces ***/
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/* MEMIO Window - always implemented */
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bridge->flags = PCI_BUS_MEMIO;
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res = &bridge->dev.resources[BRIDGE_RES_MEMIO];
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res->flags = PCI_RES_MEMIO;
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res->bar = BRIDGE_RES_MEMIO;
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PCI_CFG_R32(pcidev, 0x20, &tmp);
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res->start = (tmp & 0xfff0) << 16;
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res->end = 1 + ((tmp & 0xfff00000) | 0xfffff);
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if (res->end <= res->start) {
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/* Window disabled */
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res->end = res->start = 0;
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}
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res->size = res->end - res->start;
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/* I/O Window - optional */
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res = &bridge->dev.resources[BRIDGE_RES_IO];
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res->bar = BRIDGE_RES_IO;
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PCI_CFG_R32(pcidev, 0x30, &tmp);
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PCI_CFG_R16(pcidev, 0x1c, &tmp16);
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if (tmp != 0 || tmp16 != 0) {
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bridge->flags |= PCI_BUS_IO;
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res->flags = PCI_RES_IO;
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if (tmp16 & 0x1) {
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bridge->flags |= PCI_BUS_IO32;
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res->flags |= PCI_RES_IO32;
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}
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res->start = (tmp & 0xffff) << 16 |
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(tmp16 & 0xf0) << 8;
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res->end = 1 + ((tmp & 0xffff0000) |
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(tmp16 & 0xf000) |
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0xfff);
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if (res->end <= res->start) {
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/* Window disabled */
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res->end = res->start = 0;
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}
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res->size = res->end - res->start;
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}
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/* MEM Window - optional */
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res = &bridge->dev.resources[BRIDGE_RES_MEM];
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res->bar = BRIDGE_RES_MEM;
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PCI_CFG_R32(pcidev, 0x24, &tmp);
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if (tmp != 0) {
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bridge->flags |= PCI_BUS_MEM;
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res->flags = PCI_RES_MEM;
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res->start = (tmp & 0xfff0) << 16;
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res->end = 1 + ((tmp & 0xfff00000) |
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0xfffff);
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if (res->end <= res->start) {
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/* Window disabled */
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res->end = res->start = 0;
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}
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res->size = res->end - res->start;
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}
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/* Scan Secondary Bus */
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pci_read_devs(bridge);
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/* Only 2 BARs for Bridges */
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maxbars = 2;
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} else {
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/* Devices have subsytem device and vendor ID */
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PCI_CFG_R16(pcidev, PCIR_SUBVEND_0,
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&dev->subvendor);
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PCI_CFG_R16(pcidev, PCIR_SUBDEV_0,
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&dev->subdevice);
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/* Normal PCI Device has max 6 BARs */
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maxbars = 6;
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}
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/* Probe BARs */
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for (i = 0; i < maxbars; i++)
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pci_read_bar(dev, i);
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pci_read_bar(dev, DEV_RES_ROM);
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/* Get System Interrupt/Vector for device.
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* 0 means no-IRQ
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*/
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PCI_CFG_R8(pcidev, PCIR_INTLINE, &dev->sysirq);
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/* Stop if not a multi-function device */
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if (func == 0) {
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pci_cfg_r8(pcidev, PCIR_HDRTYPE, &header);
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if ((header & PCIM_MFDEV) == 0)
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break;
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}
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}
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}
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if (bus->num == 0)
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bus->sord = max_sord;
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}
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int pci_config_read(void)
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{
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pci_system_type = PCI_SYSTEM_HOST;
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/* Find all devices and buses */
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pci_hb.flags = PCI_BUS_IO|PCI_BUS_MEMIO|PCI_BUS_MEM;
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pci_hb.dev.flags = PCI_DEV_BRIDGE;
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pci_read_devs(&pci_hb);
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pci_bus_cnt = pci_hb.sord + 1;
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if (pci_hb.devs == NULL)
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return 0;
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return 0;
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}
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