forked from Imagelibrary/rtems
331 lines
13 KiB
ArmAsm
331 lines
13 KiB
ArmAsm
/*!@file
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*
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* @brief Initialization code to set up the CPU and call boot_card()
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*
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* This "BSP" targets the Xilinx Virtex XC4VFX60 and related parts. This
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* BSP makes no assumptions on what firmware is loaded into the FPGA.
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*
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* Provides the .entry section code. This is the first code to run in
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* the PPC after download to RAM. Excecution in this case starts at
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* 'download_entry'.
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*
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* The entrypoint 'start' is provided for the case where a bootloader has
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* initialized the CPU, and all that remains to do is to set up a C
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* environment and call boot_card.
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*
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* Derived from virtex dlentry and others.
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*
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* IBM refers to the version of the processor as PPC405F5.
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* The processor version register returns 0x20011470.
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* References:
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* PowerPC Processor Reference Guide UG011 (v1.3)
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* http://www.xilinx.com/support/documentation/user_guides/ug011.pdf
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*
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* PowerPC Block Reference Guide
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* http://www.xilinx.com/support/documentation/user_guides/ug018.pdf
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*
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* PowerPC errata
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* ftp://ftp.xilinx.com/pub/documentation/misc/ppc405f6v5_2_0.pdf
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*
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* PowerPC 405-S Embedded Processor Core User's Manual (Version 1.2)
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* https://www-01.ibm.com/chips/techlib/techlib.nsf/products/PowerPC_405_Embedded_Cores
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*
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* @author Richard Claus <claus@SLAC.Stanford.edu>
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*
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* @date March 4, 2011 -- Created
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*
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* $Revision: 674 $
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*
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* @verbatim Copyright 2011
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* by
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* The Board of Trustees of the
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* Leland Stanford Junior University.
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* All rights reserved.
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*
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* Work supported by the U.S. Department of Energy under contract
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* DE-AC03-76SF00515.
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*
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* Disclaimer Notice
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*
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* The items furnished herewith were developed under the sponsorship
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* of the U.S. Government. Neither the U.S., nor the U.S. D.O.E., nor the
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* Leland Stanford Junior University, nor their employees, makes any war-
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* ranty, express or implied, or assumes any liability or responsibility
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* for accuracy, completeness or usefulness of any information, apparatus,
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* product or process disclosed, or represents that its use will not in-
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* fringe privately-owned rights. Mention of any product, its manufactur-
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* er, or suppliers shall not, nor is it intended to, imply approval, dis-
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* approval, or fitness for any particular use. The U.S. and the Univer-
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* sity at all times retain the right to use and disseminate the furnished
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* items for any purpose whatsoever. Notice 91 02 01
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*
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* @endverbatim
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*/
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#include <rtems/asm.h>
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#include <rtems/powerpc/powerpc.h>
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/*
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* The virtex ELF link scripts support some special sections:
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* .entry The actual entry point
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* .vectors The section containing the interrupt entry veneers.
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*/
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/*
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* Downloaded code loads the vectors separately to 0x00000100,
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* so .entry can be over 256 bytes.
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*
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* The other sections are linked in the following order:
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* .entry
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* .text
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* .data
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* .bss
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* see linker command file for section placement
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*
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* The initial stack is set to _ISR_Stack_area_end.
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*
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*/
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.section .entry
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PUBLIC_VAR (download_entry)
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PUBLIC_VAR (__rtems_entry_point)
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SYM(download_entry):
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SYM(__rtems_entry_point):
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b startupDow /* Entry point used by xmd dow command */
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PUBLIC_VAR (start)
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SYM(start):
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b startupBL /* Entry point used by bootLoader */
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base_addr:
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/*-------------------------------------------------------------------
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* Parameters from linker
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*-----------------------------------------------------------------*/
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toc_pointer:
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.long __got_start
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bss_length:
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.long __bss_size
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bss_addr:
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.long __bss_start
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stack_top:
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.long _ISR_Stack_area_end
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dccr_contents:
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.long __dccr
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iccr_contents:
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.long __iccr
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sgr_contents:
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.long __sgr
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/*-------------------------------------------------------------------
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* Setup iccr, sgr, msr, cccr0, dcwr, dccr and clear bss
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*-----------------------------------------------------------------*/
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startupDow:
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/*-------------------------------------------------------------------
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* Load the parameter table base address
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*------------------------------------------------------------------*/
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lis r1, base_addr@h
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ori r1,r1,base_addr@l
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/* -------------------------------------------------------------------
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* Clear the Machine State Register's Critical and External
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* interrupt enables.
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*------------------------------------------------------------------*/
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mfmsr r3
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lis r0, 0x00028000@h
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ori r0,r0,0x00028000@l
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andc r3,r3,r0
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mtmsr r3
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sync
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/* -------------------------------------------------------------------
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* Initialize the memory system.
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*------------------------------------------------------------------*/
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li r0,0
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/* Set the Storage Guarded Register. */
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lwz r2,sgr_contents-base_addr(r1)
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mtsgr r2
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/* Configure endianness, compression */
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lis r0,0x00000000@h // Endianess value
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mtsler r0
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lis r0,0x00000000@h // Compression value
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mtsu0r r0
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/* Invalidate the entire instruction cache. */
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iccci r0,r0
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/* Set the Instruction Cache Cacheability Register. */
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lwz r2,iccr_contents-base_addr(r1)
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mticcr r2
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isync
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/*-------------------------------------------------------------------
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* Tell the processor where the exception vector table will be.
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*------------------------------------------------------------------*/
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.extern SYM(__vectors)
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lis r2, __vectors@h /* set EVPR exc. vector prefix */
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mtevpr r2
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/*-------------------------------------------------------------------
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* Set up the debug register to freeze timers on debug events.
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*------------------------------------------------------------------*/
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mfdbcr0 r2
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ori r2,r2,0x0001
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mtdbcr0 r2
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isync
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/* Select whether APU, Wait Enable, interrupts/exceptions and address
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translation should be enabled when application starts */
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lis r0,0x00000000@h /* SRR1 value */
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mtsrr1 r0 /* Potentially: 0x80000000 >> 6 is APU */
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/* Configure timer facilities */
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mttbl r0 /* Clear Timebase to prevent Fixed Interval.. */
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mttbu r0 /* ..timer and Watchdog Timer exceptions */
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mtpit r0 /* Programmable interval timer */
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li r2,-1 /* -1 to clear TSR */
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mttsr r2 /* Timer status register */
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/* Clear out stale values in certain registers to avoid confusion */
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mtcrf 0xff,r0 /* Need for simulation */
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mtctr r0 /* Counter register */
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mtxer r0 /* Fixed-point exception register */
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mtesr r0 /* Exception syndrome register */
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mtdear r0 /* Data exception address register */
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mtmcsr r0 /* Machine check syndrome register */
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/* Invalidate the data cache */
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li r2,0 /* Start address */
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li r3,0x100 /* Number of cache lines */
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mtctr r3 /* Transfer data cache congruence class count to CTR */
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1: dccci 0,r2 /* Invalidate this congruence class */
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addi r2,r2,0x20 /* Point to next congruence class */
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bdnz 1b /* Decrement counter and loop whilst not zero */
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/* -------------------------------------------------------------------
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* Set Core Configuration Register 0 as follows:
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* sum: 0x02700E00
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* bit 1 off: as told by ppc405 errata to avoid CPU_213 ppc bug
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* bit 3 off: as told by ppc405 errata to avoid CPU_213 ppc bug
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(Note added later: PPC405F6 is not subject to CPU_213.)
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* bit 1 on: Xilinx: CR 203746 Patch for PPC405 errata (RiC 12/8/11)
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* bit 2 on: Xilinx: CR 203746 Patch for PPC405 errata (RiC 12/8/11)
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* bit 6 on: load word as line
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* bit 7 off: load misses allocate cache line
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* bit 8 off: store misses allocate cache line
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* bit 9-11 on: default settings to do with plb priority
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* bit 20 on: prefetching for cacheable regions
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* bit 21 on: prefetching for non-cacheable regions
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* bit 22 on: request size of non-cacheable inst fetches is 8 words
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* bit 23 off: fetch misses allocate cache line
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*------------------------------------------------------------------*/
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lis r5, 0x52700E00@h
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ori r5,r5,0x52700E00@l
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/* -------------------------------------------------------------------
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* To change CCR0 we make sure the code writing to it is
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* running from the I-cache. This is needed because changing some
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* CCR0 fields will cause a hang if the processor is trying to
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* access memory at the same time.
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*------------------------------------------------------------------*/
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lis r4, 2f@h
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ori r4,r4,2f@l
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icbt r0,r4
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b 2f
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.align 5 /* New cache line (32 bytes each) */
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2:
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icbt r0,r4 /* Put this line into the I-cache. */
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isync
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mtccr0 r5
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isync
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b 3f
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.align 5
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3:
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/* Set the Data Cache Write-Through Register for no write-through, i.e., for write-back. */
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li r0,0
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mtdcwr r0
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/* Set the Data Cache Cacheablility Register. */
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lwz r0,dccr_contents-base_addr(r1)
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mtdccr r0
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isync
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/* Fall through */
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/* -------------------------------------------------------------------
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* If a bootloader has run that has already performed some
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* initialization, which among other things has loaded
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* this code into memory and jumped to start above, the initialization
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* above does not need to be done. Execution thus resumes here.
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*------------------------------------------------------------------*/
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startupBL:
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/* -------------------------------------------------------------------
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* Note that some initialization has already been performed by the
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* bootloader code in Block RAM, which among other things has loaded
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* this code into memory and jumped to start above.
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*------------------------------------------------------------------*/
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/*-------------------------------------------------------------------
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* Load the parameter table base address
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*------------------------------------------------------------------*/
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lis r1, base_addr@h
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ori r1,r1,base_addr@l
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/*-------------------------------------------------------------------
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* Setup stack for RTEMS and call boot_card(). From this
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* point forward registers will be used in accordance with the
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* PowerPC EABI.
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*
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* boot_card() supervises the initialization of RTEMS and the C
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* library. It calls bsp_start(), etc.
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*------------------------------------------------------------------*/
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lwz r2,toc_pointer-base_addr(r1) /* set r2 to toc */
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lwz r1,stack_top-base_addr(r1) /* set r1 to stack_top */
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/* Align as required by ABI */
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li r3,PPC_STACK_ALIGNMENT-1
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andc r1,r1,r3
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/*-------------------------------------------------------------------
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* Set up r2 and r13. Upon entry r1 must have a nonzero value
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* as it will be stored in an "init done" flag. Stupid but true.
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* r1 must also be set up as a stack pointer as __eabi() jumps
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* to __init() which has a standard function prolog.
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*------------------------------------------------------------------*/
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bl __eabi
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/*-------------------------------------------------------------------
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* Zero the .bss, .sbss and .sbss2 sections.
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* Must have r2 and r13 properly set.
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*------------------------------------------------------------------*/
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bl zero_bss
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/*-------------------------------------------------------------------
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* Create a minimal stack frame for this code, the caller of boot_card().
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*------------------------------------------------------------------*/
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addi r1,r1, -PPC_MINIMUM_STACK_FRAME_SIZE
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xor r3,r3,r3
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stw r3,0(r1) /* Terminate the chain of stack frames. */
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stw r3,4(r1)
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stw r3,8(r1)
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stw r3,12(r1)
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lis r5,environ@ha
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la r5,environ@l(r5) /* environp */
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/*-------------------------------------------------------------------
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* Call boot_card() with its arguments, the command-line pointer and
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* the argument count, set to NULL.
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*------------------------------------------------------------------*/
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li r4,0 /* argv */
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li r3,0 /* argc */
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.extern SYM (boot_card)
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b SYM (boot_card)
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