forked from Imagelibrary/rtems
ff081aee72
Rename * _Configuration_Interrupt_stack_area_begin in _ISR_Stack_area_begin, * _Configuration_Interrupt_stack_area_end in _ISR_Stack_area_end, and * _Configuration_Interrupt_stack_size in _ISR_Stack_size. Move definitions to <rtems/score/isr.h>. The new names are considerable shorter and in the right namespace. Update #3459.
91 lines
2.3 KiB
C
91 lines
2.3 KiB
C
/*
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* Copyright (c) 2012, 2017 embedded brains GmbH. All rights reserved.
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*
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* embedded brains GmbH
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* Dornierstr. 4
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* 82178 Puchheim
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* Germany
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* <rtems@embedded-brains.de>
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#include <rtems/config.h>
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#include <rtems/counter.h>
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#include <bsp.h>
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#include <bsp/vectors.h>
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#include <bsp/bootcard.h>
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#include <bsp/irq-generic.h>
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#include <bsp/linker-symbols.h>
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LINKER_SYMBOL(bsp_exc_vector_base);
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/*
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* Configuration parameter for clock driver. The Trace32 PowerPC simulator has
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* an odd decrementer frequency. The time base frequency is one tick per
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* instruction. The decrementer frequency is one tick per ten instructions.
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* The clock driver assumes that the time base and decrementer frequencies are
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* equal. For now we simulate processor that issues 10000000 instructions per
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* second.
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*/
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uint32_t bsp_time_base_frequency = 10000000;
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#define MTIVPR(base) \
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__asm__ volatile ("mtivpr %0" : : "r" (base))
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#define VECTOR_TABLE_ENTRY_SIZE 16
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#define MTIVOR(vec, offset) \
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do { \
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__asm__ volatile ("mtspr " RTEMS_XSTRING(vec) ", %0" : : "r" (offset)); \
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offset += VECTOR_TABLE_ENTRY_SIZE; \
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} while (0)
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static void t32mppc_initialize_exceptions(void)
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{
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uintptr_t addr;
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ppc_exc_initialize_interrupt_stack(
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(uintptr_t) _ISR_Stack_area_begin
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);
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addr = (uintptr_t) bsp_exc_vector_base;
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MTIVPR(addr);
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MTIVOR(BOOKE_IVOR0, addr);
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MTIVOR(BOOKE_IVOR1, addr);
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MTIVOR(BOOKE_IVOR2, addr);
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MTIVOR(BOOKE_IVOR3, addr);
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MTIVOR(BOOKE_IVOR4, addr);
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MTIVOR(BOOKE_IVOR5, addr);
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MTIVOR(BOOKE_IVOR6, addr);
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MTIVOR(BOOKE_IVOR7, addr);
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MTIVOR(BOOKE_IVOR8, addr);
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MTIVOR(BOOKE_IVOR9, addr);
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MTIVOR(BOOKE_IVOR10, addr);
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MTIVOR(BOOKE_IVOR11, addr);
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MTIVOR(BOOKE_IVOR12, addr);
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MTIVOR(BOOKE_IVOR13, addr);
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MTIVOR(BOOKE_IVOR14, addr);
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MTIVOR(BOOKE_IVOR15, addr);
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MTIVOR(BOOKE_IVOR32, addr);
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MTIVOR(BOOKE_IVOR33, addr);
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MTIVOR(BOOKE_IVOR34, addr);
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MTIVOR(BOOKE_IVOR35, addr);
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}
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uint32_t _CPU_Counter_frequency(void)
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{
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return bsp_time_base_frequency;
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}
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void bsp_start(void)
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{
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get_ppc_cpu_type();
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get_ppc_cpu_revision();
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t32mppc_initialize_exceptions();
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bsp_interrupt_initialize();
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}
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