forked from Imagelibrary/rtems
101 lines
2.9 KiB
C
101 lines
2.9 KiB
C
/* pci_interface.c
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*
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* Copyright 2004, 2006, 2007 All rights reserved. (NDA items)
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* Brookhaven National Laboratory and Shuchen Kate Feng <feng1@bnl.gov>
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution.
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*
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* 8/17/2006 : S. Kate Feng
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* uses in_le32()/out_le32(), instead of inl()/outl() for compatibility.
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*
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* 11/2008 : Enable "PCI Read Agressive Prefetch",
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* "PCI Read Line Agressive Prefetch", and
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* "PCI Read Multiple Agressive Prefetch" to improve the
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* performance of the PCI based applications (e.g. 1GHz NIC).
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*/
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#include <libcpu/io.h>
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#include <rtems/bspIo.h> /* printk */
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#include <bsp.h>
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#include <bsp/pci.h>
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#include <bsp/gtreg.h>
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#include <bsp/gtpcireg.h>
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#include <inttypes.h>
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#define PCI_DEBUG 0
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#if 0
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#define CPU2PCI_ORDER
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#define PCI2CPU_ORDER
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#endif
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/* PCI Read Agressive Prefetch Enable (1<<16 ),
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* PCI Read Line Agressive Prefetch Enable( 1<<17),
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* PCI Read Multiple Agressive Prefetch Enable (1<<18).
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*/
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#ifdef PCI2CPU_ORDER
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#define PCI_ACCCTLBASEL_VALUE 0x01079000
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#else
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#define PCI_ACCCTLBASEL_VALUE 0x01071000
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#endif
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#define ConfSBDis 0x10000000 /* 1: disable, 0: enable */
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#define IOSBDis 0x20000000 /* 1: disable, 0: enable */
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#define ConfIOSBDis 0x30000000
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#define CpuPipeline 0x00002000 /* optional, 1:enable, 0:disable */
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/* CPU to PCI ordering register */
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#define DLOCK_ORDER_REG 0x2D0 /* Deadlock and Ordering register */
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#define PCI0OrEn 0x00000001
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#define PCI1OrEn 0x00000020
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#define PCIOrEn 0x40000000
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#define PCIOrEnMASK 0x40000021
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#define CNT_SYNC_REG 0x2E0 /* Counters and Sync Barrier register */
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#define L0SyncBar 0x00001000
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#define L1SyncBar 0x00002000
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#define DSyncBar 0x00004000
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#define SyncBarMode 0x00008000
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#define SyncBarMASK 0x0000f000
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#define WRTBK_PRIO_BUFFER 0x2d8 /* writback priority and buffer depth */
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#define ADDR_PIPELINE 0x00020000
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void pciAccessInit(void);
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void pci_interface(void)
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{
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#ifdef CPU2PCI_ORDER
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/* MOTLOad deafult : 0x07ff8600 */
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out_le32((volatile uint32_t *)(GT64x60_REG_BASE+CNT_SYNC_REG), 0x07fff600);
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#endif
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/* asserts SERR upon various detection */
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out_le32((volatile uint32_t *)(GT64x60_REG_BASE+0xc28), 0x3fffff);
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pciAccessInit();
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}
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void pciAccessInit(void)
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{
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unsigned int PciLocal, data;
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for (PciLocal=0; PciLocal < 2; PciLocal++) {
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data = in_le32((volatile uint32_t *)(GT64x60_REG_BASE+PCI0_ACCESS_CNTL_BASE0_LOW+(PciLocal * 0x80)));
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#if 0
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printk("PCI%d_ACCESS_CNTL_BASE0_LOW was 0x%x\n",PciLocal,data);
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#endif
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data |= PCI_ACCCTLBASEL_VALUE;
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data &= ~0x300000;
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out_le32((volatile uint32_t *)(GT64x60_REG_BASE+PCI0_ACCESS_CNTL_BASE0_LOW+(PciLocal * 0x80)), data);
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#if 0
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printf("PCI%d_ACCESS_CNTL_BASE0_LOW now 0x%" PRIx32 "\n",PciLocal,in_le32((volatile uint32_t *)(GT64x60_REG_BASE+PCI0_ACCESS_CNTL_BASE0_LOW+(PciLocal * 0x80))));
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#endif
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}
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}
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