forked from Imagelibrary/rtems
ff081aee72
Rename * _Configuration_Interrupt_stack_area_begin in _ISR_Stack_area_begin, * _Configuration_Interrupt_stack_area_end in _ISR_Stack_area_end, and * _Configuration_Interrupt_stack_size in _ISR_Stack_size. Move definitions to <rtems/score/isr.h>. The new names are considerable shorter and in the right namespace. Update #3459.
292 lines
5.6 KiB
ArmAsm
292 lines
5.6 KiB
ArmAsm
/**
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* @file
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*
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* @ingroup mpc55xx_asm
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*
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* @brief Boot and system start code.
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*/
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/*
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* Copyright (c) 2008-2012 embedded brains GmbH. All rights reserved.
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*
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* embedded brains GmbH
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* Obere Lagerstr. 30
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* 82178 Puchheim
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* Germany
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* <rtems@embedded-brains.de>
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#include <bspopts.h>
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#include <bsp/linker-symbols.h>
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#include <libcpu/powerpc-utility.h>
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#if MPC55XX_CHIP_FAMILY != 551
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#define HAS_SPE
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#endif
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#if MPC55XX_CHIP_FAMILY == 564
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#define INIT_REGISTERS_FOR_LSM
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#endif
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#ifdef HAS_SPE
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#define ZERO_GPR(reg) evxor reg, reg, reg
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#else
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#define ZERO_GPR(reg) xor reg, reg, reg
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#endif
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.extern __eabi
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.extern boot_card
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.extern bsp_ram_start
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.extern mpc55xx_start_config_mmu_early
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.extern mpc55xx_start_config_mmu_early_count
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.extern mpc55xx_start_early
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.globl _start
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.globl mpc55xx_start_load_section
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.globl mpc55xx_start_mmu_apply_config
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#ifdef MPC55XX_BOOTFLAGS
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.globl mpc55xx_bootflag_0
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.globl mpc55xx_bootflag_1
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#endif
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.section ".bsp_start_text", "ax"
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/* BAM: RCHW */
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.int 0x005a0000
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/* BAM: Address of start instruction */
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.int _start
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#ifdef MPC55XX_BOOTFLAGS
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/*
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* We skip over the next two boot flag words to the next 64-bit
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* aligned start address. It is 64-bit aligned to play well with
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* FLASH programming. These boot flags can be set by debuggers
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* and emulators to customize boot. Currently bit0 of
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* bootflag_0 means to "skip setting up the MMU", allowing
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* external MMU setup in a debugger before branching to 0x10.
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* This can be used e.g., to map FLASH into RAM.
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*/
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mpc55xx_bootflag_0:
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.int 0xffffffff
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mpc55xx_bootflag_1:
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.int 0xffffffff
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#endif
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_start:
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#ifdef MPC55XX_ENABLE_START_PROLOGUE
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bl mpc55xx_start_prologue
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#endif
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#ifdef MPC55XX_NEEDS_LOW_LEVEL_INIT
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/* Enable SPE */
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#ifdef HAS_SPE
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mfmsr r3
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oris r3, r3, MSR_SPE >> 16
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mtmsr r3
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isync
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#endif
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/*
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* Initialization of core registers according to "e200z4 Power
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* Architecture Core Reference Manual" section 2.6 "Reset Settings"
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* table 2-16 "Reset Settings of e200 Resources". This is necessary
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* for lock step mode (LSM).
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*/
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ZERO_GPR(r0)
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#ifdef INIT_REGISTERS_FOR_LSM
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ZERO_GPR(r1)
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ZERO_GPR(r2)
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ZERO_GPR(r4)
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ZERO_GPR(r5)
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ZERO_GPR(r6)
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ZERO_GPR(r7)
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ZERO_GPR(r8)
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ZERO_GPR(r9)
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ZERO_GPR(r10)
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ZERO_GPR(r11)
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ZERO_GPR(r12)
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ZERO_GPR(r13)
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ZERO_GPR(r14)
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ZERO_GPR(r15)
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ZERO_GPR(r16)
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ZERO_GPR(r17)
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ZERO_GPR(r18)
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ZERO_GPR(r19)
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ZERO_GPR(r20)
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ZERO_GPR(r21)
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ZERO_GPR(r22)
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ZERO_GPR(r23)
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ZERO_GPR(r24)
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ZERO_GPR(r25)
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ZERO_GPR(r26)
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ZERO_GPR(r27)
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ZERO_GPR(r28)
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ZERO_GPR(r29)
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ZERO_GPR(r30)
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ZERO_GPR(r31)
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mtcrf 0xff, r0
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mtcsrr0 r0
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mtcsrr1 r0
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mtctr r0
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mtspr FSL_EIS_DBCNT, r0
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mtspr DEAR_BOOKE, r0
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mtdec r0
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mtspr BOOKE_DECAR, r0
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mtspr FSL_EIS_DSRR0, r0
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mtspr FSL_EIS_DSRR1, r0
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mtspr BOOKE_DVC1, r0
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mtspr BOOKE_DVC2, r0
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mtspr BOOKE_IVPR, r0
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mtlr r0
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mtspr FSL_EIS_MCAR, r0
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mtmcsrr0 r0
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mtmcsrr1 r0
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mtspr SPRG0, r0
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mtspr SPRG1, r0
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mtspr SPRG2, r0
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mtspr SPRG3, r0
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mtspr SPRG4, r0
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mtspr SPRG5, r0
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mtspr SPRG6, r0
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mtspr SPRG7, r0
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mtspr FSL_EIS_SPRG8, r0
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mtspr FSL_EIS_SPRG9, r0
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mtsrr0 r0
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mtsrr1 r0
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mtspr USPRG0, r0
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#ifdef HAS_SPE
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evmra r0, r0
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#endif
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#endif /* INIT_REGISTERS_FOR_LSM */
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mtspr TBWL, r0
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mtspr TBWU, r0
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/* Enable time base */
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mfspr r3, HID0
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ori r3, r3, 0x4000
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mtspr HID0, r3
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/*
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* Enable branch prediction.
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*
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* Errata e4396: e200z7: Erroneous Address Fetch
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*
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* The propose workaround does not work.
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*/
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#if MPC55XX_CHIP_FAMILY != 567
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LWI r3, FSL_EIS_BUCSR_BBFI | FSL_EIS_BUCSR_BALLOC_ALL | FSL_EIS_BUCSR_BPRED_NOT_TAKEN | FSL_EIS_BUCSR_BPEN
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mtspr FSL_EIS_BUCSR, r3
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#endif
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#endif /* MPC55XX_NEEDS_LOW_LEVEL_INIT */
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/* MMU early initialization */
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LA r3, mpc55xx_start_config_mmu_early
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LW r4, mpc55xx_start_config_mmu_early_count
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bl mpc55xx_start_mmu_apply_config
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#ifdef MPC55XX_NEEDS_LOW_LEVEL_INIT
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/* Initialize intermediate stack (ECC) */
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LA r3, bsp_ram_start
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addi r4, r3, MPC55XX_EARLY_STACK_SIZE
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zero_intermediate_stack_loop:
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#ifdef HAS_SPE
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evstdd r0, 0(r3)
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evstdd r0, 8(r3)
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evstdd r0, 16(r3)
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evstdd r0, 24(r3)
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#else
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stw r0, 0(r3)
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stw r0, 4(r3)
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stw r0, 8(r3)
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stw r0, 12(r3)
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stw r0, 16(r3)
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stw r0, 20(r3)
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stw r0, 24(r3)
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stw r0, 28(r3)
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#endif
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addi r3, r3, 32
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cmpw cr7, r3, r4
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bne cr7, zero_intermediate_stack_loop
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subi r1, r3, 16
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#endif /* MPC55XX_NEEDS_LOW_LEVEL_INIT */
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/* Next steps in C */
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bl mpc55xx_start_early
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/* Initialize start stack */
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LA r1, _ISR_Stack_area_end
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subi r1, r1, 16
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li r0, 0
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stw r0, 0(r1)
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/*
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* Load sections. This must be performed after the stack switch
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* because it may overwrite the initial stack.
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*/
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LA r3, bsp_section_fast_text_begin
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LA r4, bsp_section_fast_text_load_begin
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LA r5, bsp_section_fast_text_size
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bl mpc55xx_start_load_section
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LA r3, bsp_section_fast_data_begin
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LA r4, bsp_section_fast_data_load_begin
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LA r5, bsp_section_fast_data_size
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bl mpc55xx_start_load_section
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LA r3, bsp_section_data_begin
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LA r4, bsp_section_data_load_begin
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LA r5, bsp_section_data_size
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bl mpc55xx_start_load_section
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/* Set up EABI and SYSV environment */
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bl __eabi
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/* Clear command line */
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li r3, 0
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/* Start RTEMS */
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bl boot_card
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/* Spin around */
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twiddle:
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b twiddle
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mpc55xx_start_mmu_apply_config:
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cmpwi cr7, r4, r0
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beqlr cr7
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mtctr r4
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mmu_init_loop:
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lwz r4, 0(r3)
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lwz r5, 4(r3)
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lwz r6, 8(r3)
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lwz r7, 12(r3)
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mtspr FSL_EIS_MAS0, r4
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mtspr FSL_EIS_MAS1, r5
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mtspr FSL_EIS_MAS2, r6
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mtspr FSL_EIS_MAS3, r7
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tlbwe
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addi r3, r3, 16
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bdnz mmu_init_loop
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blr
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mpc55xx_start_load_section:
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cmpw cr7, r3, r4
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beqlr cr7
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b memcpy
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