forked from Imagelibrary/rtems
105 lines
2.6 KiB
C
105 lines
2.6 KiB
C
/**
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* @file
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*
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* @ingroup RTEMSBSPsPowerPCMPC55XX
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*
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* @brief Clock and FMPLL initialization code.
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*/
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/*
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* Copyright (c) 2008-2011 embedded brains GmbH. All rights reserved.
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*
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* embedded brains GmbH
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* Obere Lagerstr. 30
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* 82178 Puchheim
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* Germany
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* <rtems@embedded-brains.de>
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rtems.org/license/LICENSE.
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*/
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#include <bsp.h>
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#include <bsp/fatal.h>
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#include <bsp/start.h>
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#include <bsp/bootcard.h>
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#include <bsp/mpc55xx-config.h>
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#ifdef MPC55XX_NEEDS_LOW_LEVEL_INIT
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#if defined(MPC55XX_HAS_FMPLL) || defined(MPC55XX_HAS_FMPLL_ENHANCED)
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static BSP_START_TEXT_SECTION void fmpll_wait_for_lock(void)
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{
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int i = 0;
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bool lock = false;
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while (!lock && i < 6000) {
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lock = FMPLL.SYNSR.B.LOCK != 0;
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++i;
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}
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if (!lock) {
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bsp_fatal(MPC55XX_FATAL_FMPLL_LOCK);
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}
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}
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#endif
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#endif
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BSP_START_TEXT_SECTION void mpc55xx_start_clock(void)
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{
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#ifdef MPC55XX_NEEDS_LOW_LEVEL_INIT
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const mpc55xx_clock_config *cfg = mpc55xx_start_config_clock;
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#ifdef MPC55XX_HAS_FMPLL
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volatile struct FMPLL_tag *fmpll = &FMPLL;
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fmpll->SYNCR.R = cfg->syncr_tmp.R;
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fmpll->SYNCR.R;
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fmpll_wait_for_lock();
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fmpll->SYNCR.R = cfg->syncr_final.R;
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fmpll->SYNCR.R;
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fmpll_wait_for_lock();
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#endif
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#ifdef MPC55XX_HAS_FMPLL_ENHANCED
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volatile struct FMPLL_tag *fmpll = &FMPLL;
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fmpll->ESYNCR2.R = cfg->esyncr2_tmp.R;
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fmpll->ESYNCR2.R;
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fmpll->ESYNCR1.R = cfg->esyncr1_final.R;
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fmpll->ESYNCR1.R;
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fmpll_wait_for_lock();
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fmpll->ESYNCR2.R = cfg->esyncr2_final.R;
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fmpll->ESYNCR2.R;
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fmpll_wait_for_lock();
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#if MPC55XX_CHIP_FAMILY == 551 || MPC55XX_CHIP_FAMILY == 566
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/* System clock supplied by PLL */
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SIU.SYSCLK.B.SYSCLKSEL = 2;
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#endif
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#endif
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#ifdef MPC55XX_HAS_MODE_CONTROL
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volatile CGM_tag *cgm = &CGM;
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size_t fmpll_count = sizeof(cfg->fmpll) / sizeof(cfg->fmpll [0]);
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size_t auxclk_count = sizeof(cfg->auxclk) / sizeof(cfg->auxclk [0]);
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size_t i = 0;
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for (i = 0; i < auxclk_count; ++i) {
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cgm->AUXCLK [i].AC_SC.R = cfg->auxclk [i].AC_SC.R;
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cgm->AUXCLK [i].AC_DC0_3.R = cfg->auxclk [i].AC_DC0_3.R;
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}
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for (i = 0; i < fmpll_count; ++i) {
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cgm->FMPLL [i].CR.R = cfg->fmpll [i].cr.R;
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cgm->FMPLL [i].MR.R = cfg->fmpll [i].mr.R;
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}
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cgm->OC_EN.R = cfg->oc_en.R;
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cgm->OCDS_SC.R = cfg->ocds_sc.R;
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#endif
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#endif
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}
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